From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E943C63793 for ; Thu, 22 Jul 2021 16:51:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B8736120C for ; Thu, 22 Jul 2021 16:51:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230435AbhGVQLO (ORCPT ); Thu, 22 Jul 2021 12:11:14 -0400 Received: from mail.kernel.org ([198.145.29.99]:48198 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230390AbhGVQGg (ORCPT ); Thu, 22 Jul 2021 12:06:36 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 83F4D61DBA; Thu, 22 Jul 2021 16:47:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1626972431; bh=xvudn0hGRP+WmZLEFWuJFAJ+NHZMuz8xxxHGzXolnOM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=crFReoHLHeNix3ygK5O/9KnwDlY2YFidD4yZxISKKQFpLs1RqYl82qKEjAa1mBMc7 aQt8pqWX3R2FIjT7tkyDeciUOWYXVqh/3GLPD8uzPy1IVVD65pSBnAG0TtDynVp/ce F66URRjEJokmV3REnkOeLXk13fZRj2Y19Hs/hEcU= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Alexandru Elisei , Robin Murphy , Punit Agrawal , Heiko Stuebner , Sasha Levin Subject: [PATCH 5.13 077/156] arm64: dts: rockchip: Update RK3399 PCI host bridge window to 32-bit address memory Date: Thu, 22 Jul 2021 18:30:52 +0200 Message-Id: <20210722155630.886680369@linuxfoundation.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210722155628.371356843@linuxfoundation.org> References: <20210722155628.371356843@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Punit Agrawal [ Upstream commit 8efe01b4386ab38a36b99cfdc1dc02c38a8898c3 ] The PCIe host bridge on RK3399 advertises a single 64-bit memory address range even though it lies entirely below 4GB. Previously the OF PCI range parser treated 64-bit ranges more leniently (i.e., as 32-bit), but since commit 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit memory addresses") the code takes a stricter view and treats the ranges as advertised in the device tree (i.e, as 64-bit). The change in behaviour causes failure when allocating bus addresses to devices connected behind a PCI-to-PCI bridge that require non-prefetchable memory ranges. The allocation failure was observed for certain Samsung NVMe drives connected to RockPro64 boards. Update the host bridge window attributes to treat it as 32-bit address memory. This fixes the allocation failure observed since commit 9d57e61bf723. Reported-by: Alexandru Elisei Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com Suggested-by: Robin Murphy Signed-off-by: Punit Agrawal Tested-by: Alexandru Elisei Link: https://lore.kernel.org/r/20210607112856.3499682-5-punitagrawal@gmail.com Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 1703817c7354..7f8081f9e30e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -227,7 +227,7 @@ <&pcie_phy 2>, <&pcie_phy 3>; phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; - ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, + ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, -- 2.30.2