From: Bjorn Helgaas <helgaas@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
Alex Williamson <alex.williamson@redhat.com>,
"Raj, Ashok" <ashok.raj@intel.com>,
"David S. Miller" <davem@davemloft.net>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, Kevin Tian <kevin.tian@intel.com>,
Marc Zyngier <maz@kernel.org>, Ingo Molnar <mingo@kernel.org>,
x86@kernel.org
Subject: Re: [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies
Date: Thu, 22 Jul 2021 16:43:50 -0500 [thread overview]
Message-ID: <20210722214350.GA349746@bjorn-Precision-5520> (raw)
In-Reply-To: <20210721191126.274946280@linutronix.de>
On Wed, Jul 21, 2021 at 09:11:26PM +0200, Thomas Gleixner wrote:
> A recent discussion about the PCI/MSI management for virtio unearthed a
> violation of the MSI-X specification vs. writing the MSI-X message: under
> certain circumstances the entry is written without being masked.
>
> While looking at that and the related violation of the x86 non-remapped
> interrupt affinity mechanism a few other issues were discovered by
> inspection.
>
> The following series addresses these.
>
> Note this does not fix the virtio issue, but while staring at the above
> problems I came up with a plan to address this. I'm still trying to
> convince myself that I can get away without sprinkling locking all over the
> place, so don't hold your breath that this will materialize tomorrow.
>
> The series is also available from git:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git irq/msi
>
> Thanks,
>
> tglx
> ---
> arch/x86/kernel/apic/io_apic.c | 6 +-
> arch/x86/kernel/apic/msi.c | 11 +++-
> arch/x86/kernel/hpet.c | 2
> drivers/pci/msi.c | 98 +++++++++++++++++++++++++++--------------
> include/linux/irq.h | 2
> kernel/irq/chip.c | 5 +-
> 6 files changed, 85 insertions(+), 39 deletions(-)
Acked-by: Bjorn Helgaas <bhelgaas@google.com> for the PCI pieces.
I'm happy to take the whole series via PCI, given an x86 ack. Or you
can merge with my ack.
next prev parent reply other threads:[~2021-07-22 21:43 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-21 19:11 [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Thomas Gleixner
2021-07-21 19:11 ` [patch 1/8] PCI/MSI: Enable and mask MSIX early Thomas Gleixner
2021-07-21 21:38 ` Raj, Ashok
2021-07-21 22:51 ` Thomas Gleixner
2021-07-22 21:43 ` Bjorn Helgaas
2021-07-27 20:33 ` Thomas Gleixner
2021-07-21 19:11 ` [patch 2/8] PCI/MSI: Mask all unused MSI-X entries Thomas Gleixner
2021-07-21 22:23 ` Raj, Ashok
2021-07-21 22:57 ` Thomas Gleixner
2021-07-22 13:46 ` Marc Zyngier
2021-07-28 10:04 ` Thomas Gleixner
2021-07-22 21:45 ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 3/8] PCI/MSI: Enforce that MSI-X table entry is masked for update Thomas Gleixner
2021-07-21 22:32 ` Raj, Ashok
2021-07-21 22:59 ` Thomas Gleixner
2021-07-22 21:46 ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 4/8] PCI/MSI: Enforce MSI[X] entry updates to be visible Thomas Gleixner
2021-07-22 21:48 ` Bjorn Helgaas
[not found] ` <CAHp75VdNi4rMuRz8UrW9Haf_Ge8KmNJ0w9ykheqkVhmpXHTUyg@mail.gmail.com>
2021-07-23 8:14 ` Marc Zyngier
2021-07-21 19:11 ` [patch 5/8] PCI/MSI: Simplify msi_verify_entries() Thomas Gleixner
2021-07-21 19:11 ` [patch 6/8] genirq: Provide IRQCHIP_AFFINITY_PRE_STARTUP Thomas Gleixner
2021-07-22 15:12 ` Marc Zyngier
2021-07-28 10:40 ` Thomas Gleixner
2021-07-21 19:11 ` [patch 7/8] x86/ioapic: Force affinity setup before startup Thomas Gleixner
2021-07-21 19:11 ` [patch 8/8] x86/msi: " Thomas Gleixner
2021-07-21 21:10 ` [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Raj, Ashok
2021-07-21 22:39 ` Thomas Gleixner
2021-07-22 15:17 ` Marc Zyngier
2021-07-22 21:43 ` Bjorn Helgaas [this message]
2021-07-27 20:38 ` Thomas Gleixner
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