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Fri, 23 Jul 2021 19:32:24 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Jul 2021 19:32:23 +0000 Received: from Asurada-Nvidia.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Jul 2021 12:32:23 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , Subject: [RFC][Patch v1 0/2] iommu/arm-smmu-v3: Add NVIDIA implementation Date: Fri, 23 Jul 2021 12:31:38 -0700 Message-ID: <20210723193140.9690-1-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c252ea11-9b8a-4399-a818-08d94e109957 X-MS-TrafficTypeDiagnostic: DM4PR12MB5229: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2021 19:32:24.7648 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c252ea11-9b8a-4399-a818-08d94e109957 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5229 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Nicolin Chen The SMMUv3 devices implemented in the Grace SoC support NVIDIA's custom CMDQ-Virtualization (CMDQV) hardware. Like the new ECMDQ feature first introduced in the ARM SMMUv3.3 specification, CMDQV adds multiple VCMDQ interfaces to supplement the single architected SMMU_CMDQ in an effort to reduce contention. This patch series adds CMDQV support to the arm-smmu-v3 driver by first borrowing the implementation infrastructure from the arm-smmu driver. The NVIDIA implementation is then introduced along with hooks allowing implmentations to specify custom issue_cmdlist methods. Additionally, the original issue_cmdlist and supporting methods in the arm-smmu-v3 driver are reworked to support alternative CMDQs. [ nicolinc: this v1 is more of base changes for CMDQV driver; while I am still integrating incremental features based on VFIO mdev, I sent these two out in order to collect comments and suggestions to see if the overall structure is promising. I will add more changes in v2 or later versions for more detailed implementations. Thank you! ] Nate Watterson (2): iommu/arm-smmu-v3: Add implementation infrastructure iommu/arm-smmu-v3: Add support for NVIDIA CMDQ-Virtualization hw MAINTAINERS | 2 + drivers/iommu/arm/arm-smmu-v3/Makefile | 2 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-impl.c | 15 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 71 +-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 15 + .../iommu/arm/arm-smmu-v3/nvidia-smmu-v3.c | 425 ++++++++++++++++++ 6 files changed, 503 insertions(+), 27 deletions(-) create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-impl.c create mode 100644 drivers/iommu/arm/arm-smmu-v3/nvidia-smmu-v3.c -- 2.17.1