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From: Jitao Shi <jitao.shi@mediatek.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Lee Jones" <lee.jones@linaro.org>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Matthias Brugger" <matthias.bgg@gmail.com>
Cc: <linux-pwm@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	<yingjoe.chen@mediatek.com>, <eddie.huang@mediatek.com>,
	<ck.hu@mediatek.com>, <stonea168@163.com>,
	<huijuan.xie@mediatek.com>, <shuijing.li@mediatek.com>,
	Jitao Shi <jitao.shi@mediatek.com>
Subject: [PATCH v6 4/5] pwm: mtk_disp: fix overflow in period and duty calcalation
Date: Sat, 24 Jul 2021 16:18:48 +0800	[thread overview]
Message-ID: <20210724081849.182108-5-jitao.shi@mediatek.com> (raw)
In-Reply-To: <20210724081849.182108-1-jitao.shi@mediatek.com>

Current calculation for period and high_width may have
64-bit overflow. state->period and rate are u64.
rate * state->period will overflow.

clk_div = div_u64(rate * state->period, NSEC_PER_SEC)
period = div64_u64(rate * state->period, div);
high_width = div64_u64(rate * state->duty_cycle, div);

This patch is to resolve it by using mul_u64_u64_div_u64().

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
 drivers/pwm/pwm-mtk-disp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c
index 599d7dd8ecab..4f6de6f24484 100644
--- a/drivers/pwm/pwm-mtk-disp.c
+++ b/drivers/pwm/pwm-mtk-disp.c
@@ -116,7 +116,7 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
 	 */
 	rate = clk_get_rate(mdp->clk_main);
-	clk_div = div_u64(rate * state->period, NSEC_PER_SEC) >>
+	clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
 			  PWM_PERIOD_BIT_WIDTH;
 	if (clk_div > PWM_CLKDIV_MAX) {
 		if (!mdp->enabled) {
@@ -127,11 +127,11 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 	}
 
 	div = NSEC_PER_SEC * (clk_div + 1);
-	period = div64_u64(rate * state->period, div);
+	period = mul_u64_u64_div_u64(state->period, rate, div);
 	if (period > 0)
 		period--;
 
-	high_width = div64_u64(rate * state->duty_cycle, div);
+	high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
 	value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
 
 	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
-- 
2.25.1

  parent reply	other threads:[~2021-07-24  8:19 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-24  8:18 [PATCH v6 0/5] fix the clks on/off mismatch issue and switch pwm-mtk-disp to atomic APIs Jitao Shi
2021-07-24  8:18 ` [PATCH v6 1/5] pwm: mtk-disp: adjust the clocks to avoid them mismatch Jitao Shi
2021-07-24  8:18 ` [PATCH v6 2/5] pwm: mtk_disp: fix force reg to working reg Jitao Shi
2021-08-04 17:12   ` Matthias Brugger
2021-07-24  8:18 ` [PATCH v6 3/5] pwm: mtk_disp: implement atomic API .apply() Jitao Shi
2021-07-24  8:18 ` Jitao Shi [this message]
2021-07-24  8:18 ` [PATCH v6 5/5] pwm: mtk_disp: implement atomic API .get_state() Jitao Shi

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