From: Bharat Bhushan <bbhushan2@marvell.com>
To: <will@kernel.org>, <mark.rutland@arm.com>, <robh+dt@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<sgoutham@marvell.com>
Cc: Bharat Bhushan <bbhushan2@marvell.com>
Subject: [PATCH 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor
Date: Mon, 26 Jul 2021 14:40:24 +0530 [thread overview]
Message-ID: <20210726091027.798-2-bbhushan2@marvell.com> (raw)
In-Reply-To: <20210726091027.798-1-bbhushan2@marvell.com>
Add binding documentation for the Marvell CN10k DDR
performance monitor unit.
Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com>
---
.../bindings/perf/marvell-cn10k-ddr.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.txt
diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.txt b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.txt
new file mode 100644
index 000000000000..a2a593e99963
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.txt
@@ -0,0 +1,15 @@
+* Marvell CN10k DDR performance monitor
+
+Required properties:
+
+- compatible: should be one of:
+ "marvell,cn10k-ddr-pmu"
+
+- reg: physical address and size
+
+Example:
+
+ ddrcpmu {
+ compatible = "marvell,cn10k-ddr-pmu";
+ reg = <0x87e1 0xc0000000 0x0 0x10000>;
+ };
--
2.17.1
next prev parent reply other threads:[~2021-07-26 9:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-26 9:10 [PATCH 0/4] cn10k DDR Performance monitor support Bharat Bhushan
2021-07-26 9:10 ` Bharat Bhushan [this message]
2021-07-29 23:29 ` [PATCH 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor Rob Herring
2021-08-03 11:38 ` [EXT] " Bharat Bhushan
2021-07-26 9:10 ` [PATCH 2/4] perf/marvell: ADD cn10k DDR PMU basic support Bharat Bhushan
2021-07-26 9:10 ` [PATCH 3/4] perf/marvell: cn10k DDR perfmon event overflow handling Bharat Bhushan
2021-07-26 9:10 ` [PATCH 4/4] perf/marvell: cn10k DDR perf event core ownership Bharat Bhushan
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