From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D6E0C4320A for ; Mon, 26 Jul 2021 14:01:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 03EA260F55 for ; Mon, 26 Jul 2021 14:01:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234362AbhGZNVL (ORCPT ); Mon, 26 Jul 2021 09:21:11 -0400 Received: from forward106o.mail.yandex.net ([37.140.190.187]:37327 "EHLO forward106o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234327AbhGZNVE (ORCPT ); Mon, 26 Jul 2021 09:21:04 -0400 Received: from myt6-2da614b3f5d3.qloud-c.yandex.net (myt6-2da614b3f5d3.qloud-c.yandex.net [IPv6:2a02:6b8:c12:5f2e:0:640:2da6:14b3]) by forward106o.mail.yandex.net (Yandex) with ESMTP id 36257506020A; Mon, 26 Jul 2021 17:01:30 +0300 (MSK) Received: from myt3-07a4bd8655f2.qloud-c.yandex.net (myt3-07a4bd8655f2.qloud-c.yandex.net [2a02:6b8:c12:693:0:640:7a4:bd86]) by myt6-2da614b3f5d3.qloud-c.yandex.net (mxback/Yandex) with ESMTP id I36awdfoTD-1THOdvb1; Mon, 26 Jul 2021 17:01:30 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1627308090; bh=UodZOI06rDrTB+iyDAnoxBqxuoxjS4F7HBFZfwph550=; h=In-Reply-To:References:Date:Subject:To:From:Message-Id:Cc; b=cAipfvoBsYgncq41Lmxb4cL09r6TunYB5OkP/TYls0LkKmAgOGfAs/ecQGF8NKESz yZrfJ0xbmoIi8irgMWyJsqHhEk3pnfUdNMLojdjK7djxRlAEYmvIVRLvpaLWWSc9mV ivzePyLvEGZpaH3SVMFMMmhWLHyNKFRJO7NIKz3M= Authentication-Results: myt6-2da614b3f5d3.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by myt3-07a4bd8655f2.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id olJ9yWy468-1S2i5Tbq; Mon, 26 Jul 2021 17:01:29 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin To: Alexander Sverdlin , Geert Uytterhoeven Cc: Nikita Shubin , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Kuninori Morimoto , alsa-devel@alsa-project.org (moderated list:SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEM...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 6/8] ASoC: cirrus: i2s: Prepare clock before using it Date: Mon, 26 Jul 2021 16:59:54 +0300 Message-Id: <20210726140001.24820-7-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210726140001.24820-1-nikita.shubin@maquefel.me> References: <20210726115058.23729-1-nikita.shubin@maquefel.me> <20210726140001.24820-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexander Sverdlin Use clk_prepare_enable()/clk_disable_unprepare() in preparation for switch to Common Clock Framework, otherwise the following is visible: WARNING: CPU: 0 PID: 97 at drivers/clk/clk.c:1011 clk_core_enable+0x9c/0xbc Enabling unprepared mclk ... Hardware name: Cirrus Logic EDB9302 Evaluation Board ... clk_core_enable clk_core_enable_lock ep93xx_i2s_hw_params snd_soc_dai_hw_params soc_pcm_hw_params snd_pcm_hw_params snd_pcm_ioctl ... Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- sound/soc/cirrus/ep93xx-i2s.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/sound/soc/cirrus/ep93xx-i2s.c b/sound/soc/cirrus/ep93xx-i2s.c index 0d26550d0df8..4d3179f03202 100644 --- a/sound/soc/cirrus/ep93xx-i2s.c +++ b/sound/soc/cirrus/ep93xx-i2s.c @@ -111,9 +111,9 @@ static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream) if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 && (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) { /* Enable clocks */ - clk_enable(info->mclk); - clk_enable(info->sclk); - clk_enable(info->lrclk); + clk_prepare_enable(info->mclk); + clk_prepare_enable(info->sclk); + clk_prepare_enable(info->lrclk); /* Enable i2s */ ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1); @@ -156,9 +156,9 @@ static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream) ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0); /* Disable clocks */ - clk_disable(info->lrclk); - clk_disable(info->sclk); - clk_disable(info->mclk); + clk_disable_unprepare(info->lrclk); + clk_disable_unprepare(info->sclk); + clk_disable_unprepare(info->mclk); } } -- 2.26.2