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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
	anshuman.khandual@arm.com, will@kernel.org,
	catalin.marinas@arm.com, james.morse@arm.com,
	mathieu.poirier@linaro.org, mike.leach@linaro.org,
	leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling
Date: Wed, 28 Jul 2021 14:52:08 +0100	[thread overview]
Message-ID: <20210728135217.591173-2-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210728135217.591173-1-suzuki.poulose@arm.com>

Add a minimal infrastructure to keep track of the errata
affecting the given TRBE instance. Given that we have
heterogeneous CPUs, we have to manage the list per-TRBE
instance to be able to apply the work around as needed.

We rely on the arm64 errata framework for the actual
description and the discovery of a given erratum, to
keep the Erratum work around at a central place and
benefit from the code and the advertisement from the
kernel. We use a local mapping of the erratum to
avoid bloating up the individual TRBE structures.
i.e, each arm64 TRBE erratum bit is assigned a new number
within the driver to track. Each trbe instance updates
the list of affected erratum at probe time on the CPU.
This makes sure that we can easily access the list of
errata on a given TRBE instance without much overhead.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-trbe.c | 48 ++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index b8586c170889..0368bf405e35 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -16,6 +16,8 @@
 #define pr_fmt(fmt) DRVNAME ": " fmt
 
 #include <asm/barrier.h>
+#include <asm/cputype.h>
+
 #include "coresight-self-hosted-trace.h"
 #include "coresight-trbe.h"
 
@@ -65,6 +67,35 @@ struct trbe_buf {
 	struct trbe_cpudata *cpudata;
 };
 
+/*
+ * TRBE erratum list
+ *
+ * We rely on the corresponding cpucaps to be defined for a given
+ * TRBE erratum. We map the given cpucap into a TRBE internal number
+ * to make the tracking of the errata lean.
+ *
+ * This helps in :
+ *   - Not duplicating the detection logic
+ *   - Streamlined detection of erratum across the system
+ *
+ * Since the erratum work arounds could be applied individually
+ * per TRBE instance, we keep track of the list of errata that
+ * affects the given instance of the TRBE.
+ */
+#define TRBE_ERRATA_MAX			0
+
+static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = {
+};
+
+/*
+ * struct trbe_cpudata: TRBE instance specific data
+ * @trbe_flag		- TRBE dirty/access flag support
+ * @tbre_align		- Actual TRBE alignment required for TRBPTR_EL1.
+ * @cpu			- CPU this TRBE belongs to.
+ * @mode		- Mode of current operation. (perf/disabled)
+ * @drvdata		- TRBE specific drvdata
+ * @errata		- Bit map for the errata on this TRBE.
+ */
 struct trbe_cpudata {
 	bool trbe_flag;
 	u64 trbe_align;
@@ -72,6 +103,7 @@ struct trbe_cpudata {
 	enum cs_mode mode;
 	struct trbe_buf *buf;
 	struct trbe_drvdata *drvdata;
+	DECLARE_BITMAP(errata, TRBE_ERRATA_MAX);
 };
 
 struct trbe_drvdata {
@@ -84,6 +116,21 @@ struct trbe_drvdata {
 	struct platform_device *pdev;
 };
 
+static void trbe_check_errata(struct trbe_cpudata *cpudata)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(trbe_errata_cpucaps); i++) {
+		if (this_cpu_has_cap(trbe_errata_cpucaps[i]))
+			set_bit(i, cpudata->errata);
+	}
+}
+
+static inline bool trbe_has_erratum(int i, struct trbe_cpudata *cpudata)
+{
+	return (i < TRBE_ERRATA_MAX) && test_bit(i, cpudata->errata);
+}
+
 static int trbe_alloc_node(struct perf_event *event)
 {
 	if (event->cpu == -1)
@@ -925,6 +972,7 @@ static void arm_trbe_probe_cpu(void *info)
 		goto cpu_clear;
 	}
 
+	trbe_check_errata(cpudata);
 	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
 	if (cpudata->trbe_align > SZ_2K) {
 		pr_err("Unsupported alignment on cpu %d\n", cpu);
-- 
2.24.1


  reply	other threads:[~2021-07-28 13:53 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-28 13:52 [PATCH 00/10] arm64: Self-hosted trace related erratum workarouds Suzuki K Poulose
2021-07-28 13:52 ` Suzuki K Poulose [this message]
2021-08-02  6:43   ` [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling Anshuman Khandual
2021-09-07  9:04     ` Suzuki K Poulose
2021-09-09  2:55       ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-07-30 10:01   ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-07-30 10:05   ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-07-30 10:53   ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-07-30 11:02   ` Anshuman Khandual
2021-07-30 14:29     ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-07-30 11:26   ` Anshuman Khandual
2021-07-30 14:31     ` Suzuki K Poulose
2021-08-02 11:21   ` Catalin Marinas
2021-08-02 11:21   ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-08-02  7:44   ` Anshuman Khandual
2021-08-02 11:22   ` Catalin Marinas
2021-08-06 12:44   ` Linu Cherian
2021-09-07  9:10     ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 08/10] coresight: trbe: Workaround TRBE errat " Suzuki K Poulose
2021-08-03 10:25   ` Anshuman Khandual
2021-09-07  9:58     ` Suzuki K Poulose
2021-09-09  4:21       ` Anshuman Khandual
2021-09-09  8:37         ` Suzuki K Poulose
2021-08-06 16:09   ` Linu Cherian
2021-09-07  9:18     ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 09/10] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-08-02  9:34   ` Anshuman Khandual
2021-08-02 11:24   ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-07-29  9:55   ` Marc Zyngier
2021-07-29 10:41     ` Suzuki K Poulose
2021-08-02  9:12       ` Anshuman Khandual
2021-08-02  9:35         ` Marc Zyngier
2021-08-03  3:51           ` Anshuman Khandual
2021-09-08 13:39             ` Suzuki K Poulose
2021-08-02 11:27   ` Catalin Marinas

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