From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D4A4C4320A for ; Thu, 29 Jul 2021 05:39:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7955D6101C for ; Thu, 29 Jul 2021 05:39:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230096AbhG2Fju (ORCPT ); Thu, 29 Jul 2021 01:39:50 -0400 Received: from mga02.intel.com ([134.134.136.20]:53209 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233945AbhG2Fjr (ORCPT ); Thu, 29 Jul 2021 01:39:47 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10059"; a="199987629" X-IronPort-AV: E=Sophos;i="5.84,278,1620716400"; d="scan'208";a="199987629" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2021 22:39:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,278,1620716400"; d="scan'208";a="418020640" Received: from bspteam04.iind.intel.com ([10.106.46.142]) by orsmga003.jf.intel.com with ESMTP; 28 Jul 2021 22:39:41 -0700 From: shruthi.sanil@intel.com To: daniel.lezcano@linaro.org, tglx@linutronix.de, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: andriy.shevchenko@linux.intel.com, kris.pan@linux.intel.com, mgross@linux.intel.com, srikanth.thokala@intel.com, lakshmi.bai.raja.subramanian@intel.com, mallikarjunappa.sangannavar@intel.com, shruthi.sanil@intel.com Subject: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer Date: Thu, 29 Jul 2021 11:09:36 +0530 Message-Id: <20210729053937.20281-2-shruthi.sanil@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210729053937.20281-1-shruthi.sanil@intel.com> References: <20210729053937.20281-1-shruthi.sanil@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Shruthi Sanil Add Device Tree bindings for the Timer IP, which can be used as clocksource and clockevent device in the Intel Keem Bay SoC. Reviewed-by: Andy Shevchenko Signed-off-by: Shruthi Sanil --- .../bindings/timer/intel,keembay-timer.yaml | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml new file mode 100644 index 000000000000..b2eb2459d09b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay SoC Timers + +maintainers: + - Shruthi Sanil + +description: | + The Intel Keem Bay timer driver supports 1 free running counter and 8 timers. + Each timer is capable of generating inividual interrupt. + Both the features are enabled through the timer general config register. + + The parent node represents the common general configuration details and + the child nodes represents the counter and timers. + +properties: + reg: + description: General configuration register address and length. + maxItems: 1 + + ranges: true + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + +required: + - reg + - ranges + - "#address-cells" + - "#size-cells" + +patternProperties: + "^counter@[0-9a-f]+$": + type: object + description: Properties for Intel Keem Bay counter + + properties: + compatible: + enum: + - intel,keembay-counter + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + required: + - compatible + - reg + - clocks + + "^timer@[0-9a-f]+$": + type: object + description: Properties for Intel Keem Bay timer + + properties: + compatible: + enum: + - intel,keembay-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #define KEEM_BAY_A53_TIM + + soc { + #address-cells = <0x2>; + #size-cells = <0x2>; + + gpt@20331000 { + reg = <0x0 0x20331000 0x0 0xc>; + ranges = <0x0 0x0 0x20330000 0xF0>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + counter@e8 { + compatible = "intel,keembay-counter"; + reg = <0xe8 0x8>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@10 { + compatible = "intel,keembay-timer"; + reg = <0x10 0xc>; + interrupts = ; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@20 { + compatible = "intel,keembay-timer"; + reg = <0x20 0xc>; + interrupts = ; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@30 { + compatible = "intel,keembay-timer"; + reg = <0x30 0xc>; + interrupts = ; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@40 { + compatible = "intel,keembay-timer"; + reg = <0x40 0xc>; + interrupts = ; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@50 { + compatible = "intel,keembay-timer"; + reg = <0x50 0xc>; + interrupts = ; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@60 { + compatible = "intel,keembay-timer"; + reg = <0x60 0xc>; + interrupts = ; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@70 { + compatible = "intel,keembay-timer"; + reg = <0x70 0xc>; + interrupts = ; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + + timer@80 { + compatible = "intel,keembay-timer"; + reg = <0x80 0xc>; + interrupts = ; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + }; + }; + }; + +... -- 2.17.1