From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BE7FC43214 for ; Fri, 30 Jul 2021 15:46:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 03B3760295 for ; Fri, 30 Jul 2021 15:46:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233011AbhG3Pqz (ORCPT ); Fri, 30 Jul 2021 11:46:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233155AbhG3Pqr (ORCPT ); Fri, 30 Jul 2021 11:46:47 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E44F7C0613D5 for ; Fri, 30 Jul 2021 08:46:42 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d1so11588356pll.1 for ; Fri, 30 Jul 2021 08:46:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HGNj9GKkPcNlrQ3u81KWmc1E6wLr3PhoH6cMUoSxMIY=; b=aFkHg2l6yaOdtV8Ca6Onrbf74caIFdI1DKRYCrMMfbe0xGMSMWUNHQ4PiC2Xz+tAkK dFnu5/uRUjjZXlmmpBrzCG1skLJiZEb43HD8O+P7iqHf+jDgRtvaGx+ms/elJxST3cVZ lNHsdsBrtQMtOVLrLmb0BtNeapnEzZ8LT8nuE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HGNj9GKkPcNlrQ3u81KWmc1E6wLr3PhoH6cMUoSxMIY=; b=sNsrK3UocRYFXVzWlizXUZEPvat6V5kuWVGYwfP7thoSdw5/36p6yEXZmUpHJQqiLu 2JTS8ChPiKU91vKHzE8/Pn/RgvSPNugrvF9AUqp7A5BX1qBZ/ZGVMmx2McTIMTFV3IDA 8/3NhHJT3atP3Ayc6b9Agji1unF3KYjCNOpQQmVZussqOy8fyIf2FnMzPDuYl7AAdS98 1QXthN6QQRI8FQgsAXddSIAywi7v2DKXR4Sfw/7r99bCK783lDtEAEnuTCXTRATe54yl xvYH5U2h+jhtZCbF1bdoew9itiss+Ys78H0xOU5qMak3yJTfn4v46WBZrRJHHKAgdvHv cn4g== X-Gm-Message-State: AOAM53266bjAZdRQzo/36WuqA4KR6pj8/a+kicvubQTGyVsN+jUQQj4e 3A1Ie3xgE/mURDXhNHpP1ePsIA== X-Google-Smtp-Source: ABdhPJx+3y28Ce4LyY9cSNNhWVuXUoPdutEn+sS5mEWeDERMUSHe6T3XxxsIUu92Fq4H0NEbRcTjBQ== X-Received: by 2002:a17:90a:d595:: with SMTP id v21mr3832821pju.50.1627660002461; Fri, 30 Jul 2021 08:46:42 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:201:3424:e0ac:5a92:d061]) by smtp.gmail.com with ESMTPSA id u188sm3175621pfc.115.2021.07.30.08.46.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 08:46:41 -0700 (PDT) From: Douglas Anderson To: dri-devel@lists.freedesktop.org Cc: devicetree@vger.kernel.org, steev@kali.org, robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com, bjorn.andersson@linaro.org, daniel@ffwll.ch, airlied@linux.ie, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, rodrigo.vivi@intel.com, sam@ravnborg.org, jonas@kwiboo.se, mripard@kernel.org, thierry.reding@gmail.com, lyude@redhat.com, linus.walleij@linaro.org, rajeevny@codeaurora.org, linux-arm-msm@vger.kernel.org, a.hajda@samsung.com, tzimmermann@suse.de, narmstrong@baylibre.com, Douglas Anderson , Sean Paul , Sandeep Panda , linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] drm/bridge: ti-sn65dsi86: Fix power off sequence Date: Fri, 30 Jul 2021 08:46:01 -0700 Message-Id: <20210730084534.v2.2.If8a8ec3bf1855cf0dbb62c005a71d6698c99c125@changeid> X-Mailer: git-send-email 2.32.0.554.ge1b32706d8-goog In-Reply-To: <20210730154605.2843418-1-dianders@chromium.org> References: <20210730154605.2843418-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When testing with a panel that's apparently a little more persnickety about the correct power sequence (specifically Samsung ATNA33XC20), we found that the ti-sn65dsi86 was doing things just slightly wrong. Looking closely at the ti-sn65dsi86's datasheet, the power off sequence is supposed to be: 1. Clear VSTREAM_ENABLE bit 2. Stop DSI stream from GPU. DSI lanes must be placed in LP11 state. 3. Program the ML_TX_MODE to 0x0 (OFF) 4. Program the DP_NUM_LANES register to 0x0 5. Clear the DP_PLL_EN bit. 6. Deassert the EN pin. 7. Remove power from supply pins Since we were doing the whole sequence in the "disable", I believe that step #2 (stopping the DSI stream from the GPU) wasn't happening. We also weren't setting DP_NUM_LANES to 0. Let's fix this. NOTE: things are a little asymmetric now. For instance, we turn the PLL on in "enable" but now we're not turning it off until "post_disable". It would seem to make sense to move the PLL turning on to "pre_enable" to match. Unfortunately, I don't believe that's allowed. It looks as if (in the non-refclk mode which probably nobody is using) we have to wait until the MIPI clock is there before we can enable the PLL. In any case, the way it is here won't really hurt--it'll just leave the PLL on a little longer. Fixes: a095f15c00e2 ("drm/bridge: add support for sn65dsi86 bridge driver") Signed-off-by: Douglas Anderson Acked-by: Robert Foss Reviewed-by: Sean Paul --- (no changes since v1) drivers/gpu/drm/bridge/ti-sn65dsi86.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 9bf889302bcc..5e932070a1c3 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -766,10 +766,6 @@ static void ti_sn_bridge_disable(struct drm_bridge *bridge) /* disable video stream */ regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); - /* semi auto link training mode OFF */ - regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); - /* disable DP PLL */ - regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); } static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata) @@ -1106,6 +1102,13 @@ static void ti_sn_bridge_post_disable(struct drm_bridge *bridge) { struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); + /* semi auto link training mode OFF */ + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); + /* Num lanes to 0 as per power sequencing in data sheet */ + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); + /* disable DP PLL */ + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); + if (!pdata->refclk) ti_sn65dsi86_disable_comms(pdata); -- 2.32.0.554.ge1b32706d8-goog