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From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
To: Vinod Koul <vkoul@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh@kernel.org>
Cc: "Krzysztof Wilczyński" <kw@linux.com>,
	"Binghui Wang" <wangbinghui@hisilicon.com>,
	"Xiaowei Song" <songxiaowei@hisilicon.com>,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-phy@lists.infradead.org
Subject: Re: [PATCH v8 00/11] Add support for Hikey 970 PCIe
Date: Sun, 1 Aug 2021 18:55:00 +0200	[thread overview]
Message-ID: <20210801185500.7fbb1849@coco.lan> (raw)
In-Reply-To: <cover.1627637745.git.mchehab+huawei@kernel.org>

Em Fri, 30 Jul 2021 11:50:03 +0200
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> escreveu:

> On this version, the DT bindings were split on a separate patch series:
> 	https://lore.kernel.org/lkml/cover.1627637448.git.mchehab+huawei@kernel.org/
> 
> The patches here should apply cleanly on the top of v5.14-rc1.
> 
> patch1 contains a PHY for Kirin 970 PCIe.
> 
> The remaining patches add support for Kirin 970 at the pcie-kirin driver, and
> add the needed logic to compile it as module and to allow to dynamically
> remove the driver in runtime.
> 
> Tested on HiKey970:
> 
>   # lspci -D -PP
>   0000:00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01)
>   0000:00:00.0/01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   0000:00:00.0/01:00.0/02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   0000:00:00.0/01:00.0/02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   0000:00:00.0/01:00.0/02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   0000:00:00.0/01:00.0/02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   0000:00:00.0/01:00.0/02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   0000:00:00.0/01:00.0/02:01.0/03:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd Device a809
>   0000:00:00.0/01:00.0/02:07.0/06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)


As a reference, this is HiKey970 with both M.2 and mini-PCIe slots with
devices:

# lspci -D -PP
0000:00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01)
0000:00:00.0/01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
0000:00:00.0/01:00.0/02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
0000:00:00.0/01:00.0/02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
0000:00:00.0/01:00.0/02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
0000:00:00.0/01:00.0/02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
0000:00:00.0/01:00.0/02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
0000:00:00.0/01:00.0/02:01.0/03:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd Device a809
0000:00:00.0/01:00.0/02:05.0/05:00.0 Network controller: Intel Corporation Centrino Advanced-N + WiMAX 6250 [Kilmer Peak] (rev 5e)
0000:00:00.0/01:00.0/02:07.0/06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)

Regards,
Mauro

Thanks,
Mauro

      parent reply	other threads:[~2021-08-01 16:55 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-30  9:50 Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 01/11] phy: HiSilicon: Add driver for Kirin 970 PCIe PHY Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 02/11] PCI: kirin: Reorganize the PHY logic inside the driver Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 03/11] PCI: kirin: Add support for a PHY layer Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 04/11] PCI: kirin: Use regmap for APB registers Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 05/11] PCI: kirin: Add support for bridge slot DT schema Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 06/11] PCI: kirin: Add Kirin 970 compatible Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 07/11] PCI: kirin: Add MODULE_* macros Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 08/11] PCI: kirin: Allow building it as a module Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 09/11] PCI: kirin: Add power_off support for Kirin 960 PHY Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 10/11] PCI: kirin: fix poweroff sequence Mauro Carvalho Chehab
2021-07-30  9:50 ` [PATCH v8 11/11] PCI: kirin: Allow removing the driver Mauro Carvalho Chehab
2021-08-01 16:55 ` Mauro Carvalho Chehab [this message]

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