From: Icenowy Zheng <icenowy@sipeed.com>
To: Rob Herring <robh+dt@kernel.org>,
Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Linus Walleij <linus.walleij@linaro.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Andre Przywara <andre.przywara@arm.com>,
Samuel Holland <samuel@sholland.org>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
Icenowy Zheng <icenowy@sipeed.com>
Subject: [PATCH 08/17] pinctrl: sunxi: add support for R329 R-PIO pin controller
Date: Mon, 2 Aug 2021 14:22:03 +0800 [thread overview]
Message-ID: <20210802062212.73220-9-icenowy@sipeed.com> (raw)
In-Reply-To: <20210802062212.73220-1-icenowy@sipeed.com>
Allwinner R320 SoC has a pin controller in the CPUS power domain.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
---
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-r329-r.c | 292 ++++++++++++++++++
3 files changed, 298 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-r329-r.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index c662e8b1b351..abd60ff8daec 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -134,4 +134,9 @@ config PINCTRL_SUN50I_R329
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_R329_R
+ bool "Support for the Allwinner R329 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index e33f7c5f1ff9..245840a7959e 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -26,5 +26,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o
obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o
obj-$(CONFIG_PINCTRL_SUN50I_R329) += pinctrl-sun50i-r329.o
+obj-$(CONFIG_PINCTRL_SUN50I_R329_R) += pinctrl-sun50i-r329-r.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-r329-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-r329-r.c
new file mode 100644
index 000000000000..dc4792c685ba
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-r329-r.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H616 R_PIO pin controller driver
+ *
+ * Copyright (C) 2020 Arm Ltd.
+ * Based on former work, which is:
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_r329_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2s"), /* LRCK */
+ SUNXI_FUNCTION(0x4, "s_dmic"), /* DATA3 */
+ SUNXI_FUNCTION(0x5, "s_pwm"), /* PWM0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2s"), /* BCLK */
+ SUNXI_FUNCTION(0x4, "s_dmic"), /* DATA2 */
+ SUNXI_FUNCTION(0x5, "s_pwm"), /* PWM1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2s_dout0"),
+ SUNXI_FUNCTION(0x3, "s_i2s_din1"),
+ SUNXI_FUNCTION(0x4, "s_dmic"), /* DATA1 */
+ SUNXI_FUNCTION(0x5, "s_pwm"), /* PWM2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2s_dout1"),
+ SUNXI_FUNCTION(0x3, "s_i2s_din0"),
+ SUNXI_FUNCTION(0x4, "s_dmic"), /* DATA0 */
+ SUNXI_FUNCTION(0x5, "s_i2c"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2s"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "s_ir"), /* RX */
+ SUNXI_FUNCTION(0x4, "s_dmic"), /* CLK */
+ SUNXI_FUNCTION(0x5, "s_i2c"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
+ SUNXI_FUNCTION(0x5, "s_pwm"), /* PWM3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
+ SUNXI_FUNCTION(0x5, "s_pwm"), /* PWM4 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_ir"), /* RX */
+ SUNXI_FUNCTION(0x4, "clock"), /* X32KFOUT */
+ SUNXI_FUNCTION(0x5, "s_pwm"), /* PWM5 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
+ SUNXI_FUNCTION(0x4, "s_ir"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
+ SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
+ SUNXI_FUNCTION(0x4, "clock"), /* X32KFOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
+ SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
+ SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */
+ SUNXI_FUNCTION(0x4, "s_i2c"), /* SDA */
+ SUNXI_FUNCTION(0x5, "s_ir"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PM_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_ir"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "clock"), /* X32KFOUT */
+ SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */
+ SUNXI_FUNCTION(0x4, "s_i2c"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PM_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nmi"),
+ SUNXI_FUNCTION(0x3, "s_ir"), /* RX */
+ SUNXI_FUNCTION(0x4, "clock"), /* X32KFOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PM_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_ir"), /* RX */
+ SUNXI_FUNCTION(0x3, "clock"), /* X32KFOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PM_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PM_EINT8 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PN_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* MDC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PN_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* MDIO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PN_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PN_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* TXCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PN_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PN_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PN_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* RXCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PN_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* RXERR */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PN_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* TXCTL/TXEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PN_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PN_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PN_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* RXCTL/CRS_DV */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PN_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PN_EINT13 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PN_EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PN_EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* EPHY-25M */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PN_EINT16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* CLKIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PN_EINT17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), /* PN_EINT18 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), /* PN_EINT19 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)), /* PN_EINT20 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)), /* PN_EINT21 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)), /* PN_EINT22 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)), /* PN_EINT23 */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_r329_r_pinctrl_data = {
+ .pins = sun50i_r329_r_pins,
+ .npins = ARRAY_SIZE(sun50i_r329_r_pins),
+ .pin_base = PL_BASE,
+ .irq_banks = 3,
+ .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+};
+
+static int sun50i_r329_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun50i_r329_r_pinctrl_data);
+}
+
+static const struct of_device_id sun50i_r329_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-r329-r-pinctrl", },
+ {}
+};
+
+static struct platform_driver sun50i_r329_r_pinctrl_driver = {
+ .probe = sun50i_r329_r_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-r329-r-pinctrl",
+ .of_match_table = sun50i_r329_r_pinctrl_match,
+ },
+};
+builtin_platform_driver(sun50i_r329_r_pinctrl_driver);
--
2.30.2
next prev parent reply other threads:[~2021-08-02 6:31 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-02 6:21 [PATCH 00/17] Basical Allwinner R329 support Icenowy Zheng
2021-08-02 6:21 ` [PATCH 01/17] rtc: sun6i: Fix time overflow handling Icenowy Zheng
2021-08-02 6:21 ` [PATCH 02/17] rtc: sun6i: Add support for linear day storage Icenowy Zheng
2021-08-02 6:21 ` [PATCH 03/17] rtc: sun6i: Add support for broken-down alarm registers Icenowy Zheng
2021-08-02 6:21 ` [PATCH 04/17] dt-bindings: rtc: sun6i: add compatible string for R329 RTC Icenowy Zheng
2021-08-06 21:39 ` Rob Herring
2021-08-02 6:22 ` [PATCH 05/17] rtc: sun6i: add support " Icenowy Zheng
2021-08-02 6:22 ` [PATCH 06/17] dt-bindings: pinctrl: document Allwinner R329 PIO and R-PIO Icenowy Zheng
2021-08-06 21:40 ` Rob Herring
2021-08-18 8:48 ` Maxime Ripard
2021-08-19 2:40 ` Samuel Holland
2021-08-02 6:22 ` [PATCH 07/17] pinctrl: sunxi: add support for R329 CPUX pin controller Icenowy Zheng
2021-08-11 9:23 ` Linus Walleij
2021-08-18 8:48 ` Maxime Ripard
2021-08-19 3:09 ` Samuel Holland
2021-08-02 6:22 ` Icenowy Zheng [this message]
2021-08-18 8:52 ` [PATCH 08/17] pinctrl: sunxi: add support for R329 R-PIO " Maxime Ripard
2021-08-19 3:22 ` Samuel Holland
2021-08-02 6:22 ` [PATCH 09/17] dt-bindings: clock: sunxi-ng: add compatibles for R329 CCUs Icenowy Zheng
2021-08-06 21:41 ` Rob Herring
2021-08-02 6:22 ` [PATCH 10/17] clk: sunxi=ng: add support for R329 R-CCU Icenowy Zheng
2021-08-06 21:42 ` Rob Herring
2021-08-18 8:50 ` Maxime Ripard
2021-08-20 0:55 ` Samuel Holland
2021-08-20 4:34 ` Jernej Škrabec
2021-08-25 14:50 ` Maxime Ripard
2021-08-25 15:03 ` Jernej Škrabec
2021-08-25 15:37 ` Maxime Ripard
2021-08-26 0:20 ` Samuel Holland
2021-08-02 6:22 ` [PATCH 11/17] clk: sunxi-ng: add support for Allwinner R329 CCU Icenowy Zheng
2021-08-06 21:42 ` Rob Herring
2021-08-20 2:41 ` Samuel Holland
2021-08-25 14:54 ` Maxime Ripard
2021-08-02 6:22 ` [PATCH 12/17] dt-bindings: mmc: sunxi-mmc: add R329 MMC compatible string Icenowy Zheng
2021-08-06 21:42 ` Rob Herring
2021-08-18 8:47 ` Maxime Ripard
2021-08-02 6:22 ` [PATCH 13/17] mmc: sunxi: add support for R329 MMC controllers Icenowy Zheng
2021-08-18 8:47 ` Maxime Ripard
2021-08-20 2:43 ` Samuel Holland
2021-08-02 6:22 ` [PATCH 14/17] dt-bindings: arm: sunxi: add compatible strings for Sipeed MaixSense Icenowy Zheng
2021-08-06 21:43 ` Rob Herring
2021-08-18 9:03 ` Maxime Ripard
2021-08-02 6:22 ` [PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC Icenowy Zheng
2021-08-18 9:01 ` Maxime Ripard
[not found] ` <74F51516-2470-4A49-972B-E19D8EDD9A3D@sipeed.com>
2021-08-19 2:32 ` Samuel Holland
2021-08-20 3:06 ` Samuel Holland
2021-08-25 15:00 ` Maxime Ripard
2021-08-20 2:59 ` Samuel Holland
2021-08-02 6:22 ` [PATCH 16/17] arm64: allwinner: dts: r329: add DTSI file for Sipeed Maix IIA Icenowy Zheng
2021-08-02 6:22 ` [PATCH 17/17] arm64: allwinner: dts: r329: add support for Sipeed MaixSense Icenowy Zheng
2021-08-10 11:04 ` [PATCH 00/17] Basical Allwinner R329 support Ulf Hansson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210802062212.73220-9-icenowy@sipeed.com \
--to=icenowy@sipeed.com \
--cc=alexandre.belloni@bootlin.com \
--cc=andre.przywara@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=jernej.skrabec@gmail.com \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-sunxi@lists.linux.dev \
--cc=mripard@kernel.org \
--cc=robh+dt@kernel.org \
--cc=samuel@sholland.org \
--cc=ulf.hansson@linaro.org \
--cc=wens@csie.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).