From: kernel test robot <lkp@intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: kbuild-all@lists.01.org,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <ben.widawsky@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
linux-kernel@vger.kernel.org,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: [cxl-cxl:pending 4/6] drivers/cxl/core/regs.c:34:14: error: implicit declaration of function 'readq'; did you mean 'readl'?
Date: Tue, 3 Aug 2021 14:04:35 +0800 [thread overview]
Message-ID: <202108031426.oySyW5eW-lkp@intel.com> (raw)
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tree: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git pending
head: 49a0a694dd717be79d05cdffbae02657d9ee56c7
commit: 2080f92eb80322d4260eb35c17722e68d50a2110 [4/6] cxl/core: Move register mapping infrastructure
config: powerpc64-randconfig-p002-20210803 (attached as .config)
compiler: powerpc-linux-gcc (GCC) 10.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/commit/?id=2080f92eb80322d4260eb35c17722e68d50a2110
git remote add cxl-cxl https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git
git fetch --no-tags cxl-cxl pending
git checkout 2080f92eb80322d4260eb35c17722e68d50a2110
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross ARCH=powerpc64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/cxl/core/regs.c: In function 'cxl_probe_component_regs':
>> drivers/cxl/core/regs.c:34:14: error: implicit declaration of function 'readq'; did you mean 'readl'? [-Werror=implicit-function-declaration]
34 | cap_array = readq(base + CXL_CM_CAP_HDR_OFFSET);
| ^~~~~
| readl
cc1: some warnings being treated as errors
vim +34 drivers/cxl/core/regs.c
8
9 /**
10 * cxl_probe_component_regs() - Detect CXL Component register blocks
11 * @dev: Host device of the @base mapping
12 * @base: Mapping containing the HDM Decoder Capability Header
13 * @map: Map object describing the register block information found
14 *
15 * See CXL 2.0 8.2.4 Component Register Layout and Definition
16 * See CXL 2.0 8.2.5.5 CXL Device Register Interface
17 *
18 * Probe for component register information and return it in map object.
19 */
20 void cxl_probe_component_regs(struct device *dev, void __iomem *base,
21 struct cxl_component_reg_map *map)
22 {
23 int cap, cap_count;
24 u64 cap_array;
25
26 *map = (struct cxl_component_reg_map) { 0 };
27
28 /*
29 * CXL.cache and CXL.mem registers are at offset 0x1000 as defined in
30 * CXL 2.0 8.2.4 Table 141.
31 */
32 base += CXL_CM_OFFSET;
33
> 34 cap_array = readq(base + CXL_CM_CAP_HDR_OFFSET);
35
36 if (FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, cap_array) != CM_CAP_HDR_CAP_ID) {
37 dev_err(dev,
38 "Couldn't locate the CXL.cache and CXL.mem capability array header./n");
39 return;
40 }
41
42 /* It's assumed that future versions will be backward compatible */
43 cap_count = FIELD_GET(CXL_CM_CAP_HDR_ARRAY_SIZE_MASK, cap_array);
44
45 for (cap = 1; cap <= cap_count; cap++) {
46 void __iomem *register_block;
47 u32 hdr;
48 int decoder_cnt;
49 u16 cap_id, offset;
50 u32 length;
51
52 hdr = readl(base + cap * 0x4);
53
54 cap_id = FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, hdr);
55 offset = FIELD_GET(CXL_CM_CAP_PTR_MASK, hdr);
56 register_block = base + offset;
57
58 switch (cap_id) {
59 case CXL_CM_CAP_CAP_ID_HDM:
60 dev_dbg(dev, "found HDM decoder capability (0x%x)\n",
61 offset);
62
63 hdr = readl(register_block);
64
65 decoder_cnt = cxl_hdm_decoder_count(hdr);
66 length = 0x20 * decoder_cnt + 0x10;
67
68 map->hdm_decoder.valid = true;
69 map->hdm_decoder.offset = CXL_CM_OFFSET + offset;
70 map->hdm_decoder.size = length;
71 break;
72 default:
73 dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id,
74 offset);
75 break;
76 }
77 }
78 }
79 EXPORT_SYMBOL_GPL(cxl_probe_component_regs);
80
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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