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Ivanov" , "Lee, Chun-Yi" , Chester Lin Subject: [PATCH 0/8] arm64: dts: initial NXP S32G2 support Date: Thu, 5 Aug 2021 14:54:21 +0800 Message-ID: <20210805065429.27485-1-clin@suse.com> X-Mailer: git-send-email 2.30.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-ClientProxiedBy: AM4PR07CA0008.eurprd07.prod.outlook.com (2603:10a6:205:1::21) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost (118.166.54.149) by AM4PR07CA0008.eurprd07.prod.outlook.com (2603:10a6:205:1::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4415.5 via Frontend Transport; Thu, 5 Aug 2021 06:54:49 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f8a7a140-3bf4-4a06-fce9-08d957ddebc0 X-MS-TrafficTypeDiagnostic: VI1PR0401MB2368: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?LpQzKP6/WoBz81LoFr0m4vbVozMIb9s06K5pSVgMCI9u58ioeLSzWtgUaNvk?= =?us-ascii?Q?c5G11iUrBKSF9tTe7JOUwAlNvlf0EBlyBIzmVc9kCz3GKRJ8gAQazOtRBgME?= =?us-ascii?Q?4mXlf878zRoCbnGPihNSdz3RbqZLizuuNdpDV9pfo53VgNIC2bzCzC0at1+p?= =?us-ascii?Q?EN4Zzk1u2S1ffh3gk/O1LGR/Vk/+SXTqbh9CitXLCBZ1CTsTUtDrCx1+SVHa?= =?us-ascii?Q?BqBosYDzQbQbbVmpXVf76VXc9qg/yybJYlR0UTysREltynJrPgwjF1i4EUAV?= =?us-ascii?Q?bfrPNvles5LHXx17kIFKBKcYmH5tt1nKVaUrOAjkF5ZvEEM/WjXJiH9C7cQ9?= =?us-ascii?Q?QJj8c0FW30t2iEDZy0jr340KQncNkXcZlCgcvdzBC5ICGLU8XMY6FvwyAlxn?= =?us-ascii?Q?+q6tdEuf3D/Q+4VTGjJhGYmrOqQ4ASP8USq94rMENB3gM/feyOLtvjXApsJk?= =?us-ascii?Q?VH3yDjs8s0qGjWCHVmXUOYYRiOWv+8gpTbSCQ+gHNPfR7W+KtmV6500o0eTF?= =?us-ascii?Q?n4I+0wJknbMI7GEUOvxr2Wpu0dhBrCExBHPAzI/+bw9lXZ96ok8cNYboM3O0?= =?us-ascii?Q?ymQRYKtHr3agmCajRD1LpvggAlN1NTqWtB/VN8qQ3qEW9vxlq/FcTZvcr39N?= =?us-ascii?Q?0G7m8sqgYx+Aipeefetv3OVHbZ/fLMW/oSySTBoj44EAHpE0RL/9X0QwSVoV?= =?us-ascii?Q?JcWCLhmCGESGCObStSRbmB3v6uuR4d/+IVLLj9pCk7aIjnLwcZaygwL7Xvgy?= =?us-ascii?Q?oLRejMXY/tgMvSXf6EWYJUNXItSnkWiReMIsMYqpXmKQ74CD/BvjWedgc4YT?= =?us-ascii?Q?XMsJ6+Dfdq5tOaql8j+TgP5SAwln/cPhy+DxYxxCsMbeU25ZrHhbZkb6qXTq?= =?us-ascii?Q?uWfXe8c+/XjS/F0DLnKZvP5qeHL5g+Q8pdInMuwmkj5zhKwtp//Ik4h6U8BZ?= =?us-ascii?Q?XkSuOUced4lPptaJGJgS0cYvFehp9QmAEJX2pwV/KZUba4WH06W1RRBU4WkT?= =?us-ascii?Q?Qzl/qIgZJBKwmjKqxFmBvVnLFinni+zJBv+20cjyAbQqcxFTnY0Zwuo9AkKZ?= =?us-ascii?Q?aJENiQeZ7o5scXfWuDMO3yzx72hbv2iII/V0Z9yQvogp4r2fTOKmHSGNt2wp?= =?us-ascii?Q?K2HIlAUhBpD23JdQXKHKGNre3B7eicwMU7oL4qmm5WlPUP4AKdxHrzkDaX0Q?= =?us-ascii?Q?i8kFPUGjid2/n2SpbfC5pRICd1omd7LBAkRZAWQudhYTjAx3wCaAYq3d/0Ig?= =?us-ascii?Q?AFbLaZtaiYotherrzKfdwvfMkNujK0LjHtNNDQf1CPXDDH+bCJNGdW9N7m16?= =?us-ascii?Q?jxmiG/14n5Ehh8JLDSisjdce?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: f8a7a140-3bf4-4a06-fce9-08d957ddebc0 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2021 06:54:50.7366 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rK8Icl1pn7iao+OqPmkPFwkHjRUieiTrAM/MfcN2P0hc/Kq6Mi9exscAzuoJpYqv X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2368 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, Here I'd like to propose a patchset, which is initial upstream support for = NXP S32G2. S32G is a processor family developed by NXP for automotive solutions= , such as vehicle networking and automotive high-performance processing. This series focuses on S32G2, which is the latest generation we can find at the moment. As the first round to support S32G2, this patchset only enables bas= ic components and interfaces the SoC must have while kernel booting, which aim= s to have minimum hardware enablement for these two boards, S32G-VNP-EVB and S32G-VNP-RDB2. The concepts of how these boards work are originated from th= e downstream kernel tree[1] developed by NXP, which provides lots of details about the SoC S32G274A and its integrated boards. This series has been verified with downstream ATF[2] & U-Boot[3] based on the ATF boot flow. Thanks, Chester [1] https://source.codeaurora.org/external/autobsps32/linux/ [2] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/ [3] https://source.codeaurora.org/external/autobsps32/u-boot/ Chester Lin (8): dt-bindings: arm: fsl: add NXP S32G2 boards dt-bindings: serial: fsl-linflexuart: convert to json-schema format dt-bindings: serial: fsl-linflexuart: Add compatible for S32G2 arm64: dts: add NXP S32G2 support arm64: dts: s32g2: add serial/uart support arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support arm64: dts: s32g2: add memory nodes for evb and rdb2 MAINTAINERS: Add an entry for NXP S32G2 boards .../devicetree/bindings/arm/fsl.yaml | 7 + .../bindings/serial/fsl,s32-linflexuart.txt | 22 --- .../bindings/serial/fsl,s32-linflexuart.yaml | 66 +++++++++ MAINTAINERS | 6 + arch/arm64/boot/dts/freescale/Makefile | 2 + arch/arm64/boot/dts/freescale/s32g2.dtsi | 129 ++++++++++++++++++ .../arm64/boot/dts/freescale/s32g274a-evb.dts | 29 ++++ .../boot/dts/freescale/s32g274a-rdb2.dts | 33 +++++ 8 files changed, 272 insertions(+), 22 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linfle= xuart.txt create mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linfle= xuart.yaml create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-evb.dts create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts --=20 2.30.0