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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Apurva Nandan <a-nandan@ti.com>
Cc: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Mark Brown <broonie@kernel.org>,
	Patrice Chotard <patrice.chotard@foss.st.com>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>, Pratyush Yadav <p.yadav@ti.com>
Subject: Re: [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode
Date: Fri, 6 Aug 2021 20:43:34 +0200	[thread overview]
Message-ID: <20210806204334.5fedea42@xps13> (raw)
In-Reply-To: <20210713130538.646-5-a-nandan@ti.com>

Hi Apurva,

Apurva Nandan <a-nandan@ti.com> wrote on Tue, 13 Jul 2021 13:05:29
+0000:

> In Octal DTR SPI mode, 2 bytes of data gets transmitted over one clock
> cycle, and half-cycle instruction phases aren't supported yet. So,
> every DTR spi_mem_op needs to have even nbytes in all phases for
> non-erratic behaviour from the SPI controller.
> 
> The odd length cmd and dummy phases get handled by spimem_setup_op()
> but the odd length address and data phases need to be handled according
> to the use case. For example in Octal DTR mode, read register operation
> has one byte long address and data phase. So it needs to extend it
> by adding a suitable extra byte in addr and reading 2 bytes of data,
> discarding the second byte.
> 
> Handle address and data phases for Octal DTR mode in read/write
> register and write volatile configuration register operations
> by adding a suitable extra byte in the address and data phase.
> 
> Create spimem_setup_reg_op() helper function to ease setting up
> read/write register operations in other functions, e.g. wait().
> 
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> ---
>  drivers/mtd/nand/spi/core.c | 26 +++++++++++++++++++++-----
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
> index 2e59faecc8f5..a5334ad34f96 100644
> --- a/drivers/mtd/nand/spi/core.c
> +++ b/drivers/mtd/nand/spi/core.c
> @@ -65,12 +65,27 @@ static void spinand_setup_op(const struct spinand_device *spinand,
>  	}
>  }
>  
> +static void spinand_setup_reg_op(const struct spinand_device *spinand,
> +				 struct spi_mem_op *op)

Same remark about the naming. In fact I believe we could have this
logic in _setup_op() (or whatever its name) and add a specific
parameter for it?

> +{
> +	if (spinand->reg_proto == SPINAND_OCTAL_DTR) {
> +		/*
> +		 * Assigning same first and second byte will result in constant
> +		 * bits on ths SPI bus between positive and negative clock edges

                           the

> +		 */
> +		op->addr.val = (op->addr.val << 8) | op->addr.val;

I am not sure to understand what you do here?

> +		op->addr.nbytes = 2;
> +		op->data.nbytes = 2;
> +	}

Space

> +	spinand_setup_op(spinand, op);
> +}
> +
>  static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
>  {
> -	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
> -						      spinand->scratchbuf);
> +	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, spinand->scratchbuf);

You can do this, but in a different commit.

>  	int ret;
>  
> +	spinand_setup_reg_op(spinand, &op);
>  	ret = spi_mem_exec_op(spinand->spimem, &op);
>  	if (ret)
>  		return ret;
> @@ -81,10 +96,10 @@ static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
>  
>  static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
>  {
> -	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg,
> -						      spinand->scratchbuf);
> +	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, spinand->scratchbuf);

Same here.

>  
> -	*spinand->scratchbuf = val;
> +	spinand_setup_reg_op(spinand, &op);
> +	memset(spinand->scratchbuf, val, op.data.nbytes);
>  	return spi_mem_exec_op(spinand->spimem, &op);
>  }
>  
> @@ -547,6 +562,7 @@ static int spinand_wait(struct spinand_device *spinand,
>  	u8 status;
>  	int ret;
>  
> +	spinand_setup_reg_op(spinand, &op);
>  	ret = spi_mem_poll_status(spinand->spimem, &op, STATUS_BUSY, 0,
>  				  initial_delay_us,
>  				  poll_delay_us,

Thanks,
Miquèl

  reply	other threads:[~2021-08-06 18:43 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2021-07-13 13:05 ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan
2021-07-14 17:06   ` Mark Brown
2021-08-23  7:57   ` Boris Brezillon
2021-07-13 13:05 ` [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan
2021-07-13 13:05 ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan
2021-08-06 18:30   ` Miquel Raynal
2021-08-20  9:52     ` Apurva Nandan
2021-08-20 12:08       ` Miquel Raynal
2021-08-23  7:11         ` Boris Brezillon
2021-08-23  7:24           ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan
2021-08-06 18:43   ` Miquel Raynal [this message]
2021-08-20 10:27     ` Apurva Nandan
2021-08-20 12:06       ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan
2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan
2021-08-06 18:54   ` Miquel Raynal
2021-08-20 10:35     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan
2021-08-06 18:58   ` Miquel Raynal
2021-08-20 10:41     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan
2021-08-06 19:01   ` Miquel Raynal
2021-08-20 11:26     ` Apurva Nandan
2021-08-20 12:14       ` Miquel Raynal
2021-08-20 13:54         ` Apurva Nandan
2021-08-20 14:38           ` Miquel Raynal
2021-08-20 15:53             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan
2021-08-06 19:05   ` Miquel Raynal
2021-08-20 11:30     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan
2021-08-06 19:06   ` Miquel Raynal
2021-08-20 11:31     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan
2021-08-06 19:08   ` Miquel Raynal
2021-08-20 11:39     ` Apurva Nandan
2021-08-20 12:18       ` Miquel Raynal
2021-08-20 13:41         ` Apurva Nandan
2021-08-20 14:17           ` Miquel Raynal
2021-08-20 15:56             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan
2021-08-06 19:12   ` Miquel Raynal
2021-08-20 11:45     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan
2021-08-06 19:14   ` Miquel Raynal
2021-08-20 11:51     ` Apurva Nandan
2021-08-20 12:02       ` Miquel Raynal
2021-08-20 13:14         ` Apurva Nandan
2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva

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