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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Apurva Nandan <a-nandan@ti.com>
Cc: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Mark Brown <broonie@kernel.org>,
	Patrice Chotard <patrice.chotard@foss.st.com>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-spi@vger.kernel.org>, Pratyush Yadav <p.yadav@ti.com>
Subject: Re: [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction
Date: Fri, 6 Aug 2021 21:08:40 +0200	[thread overview]
Message-ID: <20210806210840.65c06b67@xps13> (raw)
In-Reply-To: <20210713130538.646-12-a-nandan@ti.com>

Hi Apurva,

Apurva Nandan <a-nandan@ti.com> wrote on Tue, 13 Jul 2021 13:05:36
+0000:

> Manufacturers like Gigadevice and Winbond are adding Power-on-Reset
> functionality in their SPI NAND flash chips. PoR instruction consists
> of a 66h command followed by 99h command, and is different from the FFh
> reset. The reset command FFh just clears the status only registers,
> while the PoR command erases all the configurations written to the
> flash and is equivalent to a power-down -> power-up cycle.
> 
> Add support for the Power-on-Reset command for any flash that provides
> this feature.
> 
> Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
> 
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> ---

[...]
				\
> @@ -218,6 +230,8 @@ struct spinand_device;
>   * reading/programming/erasing when the RESET occurs. Since we always
>   * issue a RESET when the device is IDLE, 5us is selected for both initial
>   * and poll delay.
> + * Power on Reset can take max upto 500 us to complete, so sleep for 1000 us

s/max upto/up to/

> + * to 1200 us safely.

I don't really get why, if the maximum is 500, then let's wait for
500us.

>   */
>  #define SPINAND_READ_INITIAL_DELAY_US	6
>  #define SPINAND_READ_POLL_DELAY_US	5
> @@ -227,6 +241,8 @@ struct spinand_device;
>  #define SPINAND_WRITE_POLL_DELAY_US	15
>  #define SPINAND_ERASE_INITIAL_DELAY_US	250
>  #define SPINAND_ERASE_POLL_DELAY_US	50
> +#define SPINAND_POR_MIN_DELAY_US	1000
> +#define SPINAND_POR_MAX_DELAY_US	1200
>  
>  #define SPINAND_WAITRDY_TIMEOUT_MS	400
>  
> @@ -351,6 +367,7 @@ struct spinand_ecc_info {
>  #define SPINAND_HAS_QE_BIT		BIT(0)
>  #define SPINAND_HAS_CR_FEAT_BIT		BIT(1)
>  #define SPINAND_HAS_OCTAL_DTR_BIT	BIT(2)
> +#define SPINAND_HAS_POR_CMD_BIT		BIT(3)
>  
>  /**
>   * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure




Thanks,
Miquèl

  reply	other threads:[~2021-08-06 19:08 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2021-07-13 13:05 ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan
2021-07-14 17:06   ` Mark Brown
2021-08-23  7:57   ` Boris Brezillon
2021-07-13 13:05 ` [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan
2021-07-13 13:05 ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan
2021-08-06 18:30   ` Miquel Raynal
2021-08-20  9:52     ` Apurva Nandan
2021-08-20 12:08       ` Miquel Raynal
2021-08-23  7:11         ` Boris Brezillon
2021-08-23  7:24           ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan
2021-08-06 18:43   ` Miquel Raynal
2021-08-20 10:27     ` Apurva Nandan
2021-08-20 12:06       ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan
2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan
2021-08-06 18:54   ` Miquel Raynal
2021-08-20 10:35     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan
2021-08-06 18:58   ` Miquel Raynal
2021-08-20 10:41     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan
2021-08-06 19:01   ` Miquel Raynal
2021-08-20 11:26     ` Apurva Nandan
2021-08-20 12:14       ` Miquel Raynal
2021-08-20 13:54         ` Apurva Nandan
2021-08-20 14:38           ` Miquel Raynal
2021-08-20 15:53             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan
2021-08-06 19:05   ` Miquel Raynal
2021-08-20 11:30     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan
2021-08-06 19:06   ` Miquel Raynal
2021-08-20 11:31     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan
2021-08-06 19:08   ` Miquel Raynal [this message]
2021-08-20 11:39     ` Apurva Nandan
2021-08-20 12:18       ` Miquel Raynal
2021-08-20 13:41         ` Apurva Nandan
2021-08-20 14:17           ` Miquel Raynal
2021-08-20 15:56             ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan
2021-08-06 19:12   ` Miquel Raynal
2021-08-20 11:45     ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan
2021-08-06 19:14   ` Miquel Raynal
2021-08-20 11:51     ` Apurva Nandan
2021-08-20 12:02       ` Miquel Raynal
2021-08-20 13:14         ` Apurva Nandan
2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva

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