From: Richard Fitzgerald <rf@opensource.cirrus.com>
To: <broonie@kernel.org>
Cc: <alsa-devel@alsa-project.org>, <patches@opensource.cirrus.com>,
<linux-kernel@vger.kernel.org>,
Richard Fitzgerald <rf@opensource.cirrus.com>
Subject: [PATCH 05/12] ASoC: cs42l42: Set correct SRC MCLK
Date: Tue, 10 Aug 2021 16:37:52 +0100 [thread overview]
Message-ID: <20210810153759.24333-6-rf@opensource.cirrus.com> (raw)
In-Reply-To: <20210810153759.24333-1-rf@opensource.cirrus.com>
According to the datasheet the SRC MCLK must be as near as possible to
(125 * sample rate). This means it should be ~6MHz for rates up to 48k
and ~12MHz for rates above that. As per datasheet table 4-21.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
---
sound/soc/codecs/cs42l42.c | 60 ++++++++++++++++++++++++++++++----------------
sound/soc/codecs/cs42l42.h | 1 +
2 files changed, 40 insertions(+), 21 deletions(-)
diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index 1893d3694570..14fd70c56891 100644
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -663,22 +663,6 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
CS42L42_FSYNC_PULSE_WIDTH_MASK,
CS42L42_FRAC1_VAL(fsync - 1) <<
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
- /* Set the sample rates (96k or lower) */
- snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
- CS42L42_FS_EN_MASK,
- (CS42L42_FS_EN_IASRC_96K |
- CS42L42_FS_EN_OASRC_96K) <<
- CS42L42_FS_EN_SHIFT);
- /* Set the input/output internal MCLK clock ~12 MHz */
- snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
- CS42L42_CLK_IASRC_SEL_MASK,
- CS42L42_CLK_IASRC_SEL_12 <<
- CS42L42_CLK_IASRC_SEL_SHIFT);
- snd_soc_component_update_bits(component,
- CS42L42_OUT_ASRC_CLK,
- CS42L42_CLK_OASRC_SEL_MASK,
- CS42L42_CLK_OASRC_SEL_12 <<
- CS42L42_CLK_OASRC_SEL_SHIFT);
if (pll_ratio_table[i].mclk_src_sel == 0) {
/* Pass the clock straight through */
snd_soc_component_update_bits(component,
@@ -741,6 +725,34 @@ static int cs42l42_pll_config(struct snd_soc_component *component)
return -EINVAL;
}
+static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
+{
+ unsigned int fs;
+
+ /* SRC MCLK must be as close as possible to 125 * sample rate */
+ if (sample_rate <= 48000)
+ fs = CS42L42_CLK_IASRC_SEL_6;
+ else
+ fs = CS42L42_CLK_IASRC_SEL_12;
+
+ /* Set the sample rates (96k or lower) */
+ snd_soc_component_update_bits(component,
+ CS42L42_FS_RATE_EN,
+ CS42L42_FS_EN_MASK,
+ (CS42L42_FS_EN_IASRC_96K |
+ CS42L42_FS_EN_OASRC_96K) <<
+ CS42L42_FS_EN_SHIFT);
+
+ snd_soc_component_update_bits(component,
+ CS42L42_IN_ASRC_CLK,
+ CS42L42_CLK_IASRC_SEL_MASK,
+ fs << CS42L42_CLK_IASRC_SEL_SHIFT);
+ snd_soc_component_update_bits(component,
+ CS42L42_OUT_ASRC_CLK,
+ CS42L42_CLK_OASRC_SEL_MASK,
+ fs << CS42L42_CLK_OASRC_SEL_SHIFT);
+}
+
static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
@@ -831,6 +843,7 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
unsigned int channels = params_channels(params);
unsigned int width = (params_width(params) / 8) - 1;
unsigned int val = 0;
+ int ret;
cs42l42->srate = params_rate(params);
cs42l42->bclk = snd_soc_params_to_bclk(params);
@@ -884,11 +897,16 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
break;
}
- /* Configure the PLL if this is the first active stream */
- if (!cs42l42->stream_use)
- return cs42l42_pll_config(component);
- else
- return 0;
+ /* Configure clocking only if this is the first active stream */
+ if (!cs42l42->stream_use) {
+ ret = cs42l42_pll_config(component);
+ if (ret)
+ return ret;
+
+ cs42l42_src_config(component, params_rate(params));
+ }
+
+ return 0;
}
static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h
index 8734f6828f3e..addb6560c649 100644
--- a/sound/soc/codecs/cs42l42.h
+++ b/sound/soc/codecs/cs42l42.h
@@ -288,6 +288,7 @@
#define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
#define CS42L42_CLK_IASRC_SEL_SHIFT 0
#define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
+#define CS42L42_CLK_IASRC_SEL_6 0
#define CS42L42_CLK_IASRC_SEL_12 1
#define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
--
2.11.0
next prev parent reply other threads:[~2021-08-10 15:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-10 15:37 [PATCH 00/12] ASoC: cs42l42: Series of bugfixes and improvements Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 01/12] ASoC: cs42l42: Use PLL for SCLK > 12.188MHz Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 02/12] ASoC: cs42l42: Don't claim to support 192k Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 03/12] ASoC: cs42l42: Always configure both ASP TX channels Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 04/12] ASoC: cs42l42: Don't reconfigure the PLL while it is running Richard Fitzgerald
2021-08-10 15:49 ` Mark Brown
2021-08-10 16:27 ` Richard Fitzgerald
2021-08-11 11:56 ` Mark Brown
2021-08-11 12:21 ` Richard Fitzgerald
2021-08-11 14:41 ` Mark Brown
2021-08-11 10:56 ` Richard Fitzgerald
2021-08-10 15:37 ` Richard Fitzgerald [this message]
2021-08-10 15:37 ` [PATCH 06/12] ASoC: cs42l42: Mark OSC_SWITCH_STATUS register volatile Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 07/12] ASoC: cs42l42: Allow time for HP/ADC to power-up after enable Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 08/12] ASoC: cs42l42: Prevent NULL pointer deref in interrupt handler Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 09/12] ASoC: cs42l42: Remove runtime_suspend/runtime_resume callbacks Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 10/12] ASoC: cs42l42: Remove redundant pll_divout member Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 11/12] ASoC: cs42l42: Add HP Volume Scale control Richard Fitzgerald
2021-08-10 15:37 ` [PATCH 12/12] ASoC: cs42l42: Add control for audio slow-start switch Richard Fitzgerald
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210810153759.24333-6-rf@opensource.cirrus.com \
--to=rf@opensource.cirrus.com \
--cc=alsa-devel@alsa-project.org \
--cc=broonie@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=patches@opensource.cirrus.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).