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Wed, 18 Aug 2021 01:10:31 -0700 Envelope-to: git@xilinx.com, arnd@arndb.de, zou_wei@huawei.com, gregkh@linuxfoundation.org, linus.walleij@linaro.org, iwamatsu@nigauri.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Received: from [10.140.6.35] (port=57498 helo=xhdsaipava40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mGGec-0008z4-GU; Wed, 18 Aug 2021 01:10:30 -0700 From: Piyush Mehta To: , , , , , , , , , CC: , , , , , , Piyush Mehta Subject: [PATCH V3 0/3] gpio: modepin: Add driver support for modepin GPIO controller Date: Wed, 18 Aug 2021 13:40:15 +0530 Message-ID: <20210818081018.2620544-1-piyush.mehta@xilinx.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 44bb71aa-3740-49d4-dd43-08d9621fb280 X-MS-TrafficTypeDiagnostic: PH0PR02MB7208: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:785; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Aug 2021 08:10:52.6604 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44bb71aa-3740-49d4-dd43-08d9621fb280 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT004.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR02MB7208 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for the zynqmp modepin GPIO controller and documented for the same. GPIO modepin driver set and get the value and status of the PS_MODE pin, based on device-tree pin configuration. These four-bits boot-mode pins are dedicated configurable as input/output. After the stabilization of the system,these mode pins are sampled. To access GPIO pins, added Xilinx ZynqMP firmware MDIO API support to set and get PS_MODE pins value and status. These APIs are interface APIs, between the mode pin controller driver and low-level API. --- Changes in v2: - Added Xilinx ZynqMP firmware MMIO API support to set and get pin value and status. - DT Documentation- Addressed review comments: Update commit message - Modepin driver- Addressed review comments: - Update APIs - Removed unwanted variables - Handle return path for probe function Review Comments: https://lore.kernel.org/linux-arm-kernel/20210624205055.GA1961487@robh.at.kernel.org/T/#u Changes in v3: - Update example in dt-bindings documentation - Update probe function return value - Remove unnecessary print and header file Review Comments: https://lore.kernel.org/linux-arm-kernel/20210805174219.3000667-1-piyush.mehta@xilinx.com/#t --- Piyush Mehta (3): firmware: zynqmp: Add MMIO read and write support for PS_MODE pin dt-bindings: gpio: zynqmp: Add binding documentation for modepin gpio: modepin: Add driver support for modepin GPIO controller .../bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 43 ++++++ drivers/firmware/xilinx/zynqmp.c | 46 +++++++ drivers/gpio/Kconfig | 12 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-zynqmp-modepin.c | 153 +++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 14 ++ 6 files changed, 269 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml create mode 100644 drivers/gpio/gpio-zynqmp-modepin.c -- 2.7.4