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Wed, 18 Aug 2021 05:01:40 -0400 (EDT) Date: Wed, 18 Aug 2021 11:01:39 +0200 From: Maxime Ripard To: Icenowy Zheng Cc: Rob Herring , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , Samuel Holland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC Message-ID: <20210818090139.rllz4fvvq3pzdkls@gilmour> References: <20210802062212.73220-1-icenowy@sipeed.com> <20210802062212.73220-16-icenowy@sipeed.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="dgafk337ems2a2tp" Content-Disposition: inline In-Reply-To: <20210802062212.73220-16-icenowy@sipeed.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --dgafk337ems2a2tp Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Aug 02, 2021 at 02:22:10PM +0800, Icenowy Zheng wrote: > Allwinner R329 is a new SoC focused on smart audio devices. >=20 > Add a DTSI file for it. >=20 > Signed-off-by: Icenowy Zheng > --- > .../arm64/boot/dts/allwinner/sun50i-r329.dtsi | 244 ++++++++++++++++++ > 1 file changed, 244 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi >=20 > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi b/arch/arm64/= boot/dts/allwinner/sun50i-r329.dtsi > new file mode 100644 > index 000000000000..bfefa2b734b0 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi > @@ -0,0 +1,244 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +// Copyright (c) 2021 Sipeed > + > +#include > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent =3D <&gic>; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + > + cpus { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + cpu0: cpu@0 { > + compatible =3D "arm,cortex-a53"; > + device_type =3D "cpu"; > + reg =3D <0>; > + enable-method =3D "psci"; > + }; > + > + cpu1: cpu@1 { > + compatible =3D "arm,cortex-a53"; > + device_type =3D "cpu"; > + reg =3D <1>; > + enable-method =3D "psci"; > + }; > + }; > + > + osc24M: osc24M_clk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <24000000>; > + clock-output-names =3D "osc24M"; > + }; > + > + psci { > + compatible =3D "arm,psci-0.2"; > + method =3D "smc"; > + }; > + > + timer { > + compatible =3D "arm,armv8-timer"; > + arm,no-tick-in-suspend; > + interrupts =3D + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > + + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > + + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, > + + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + soc { > + compatible =3D "simple-bus"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges; > + > + pio: pinctrl@2000400 { > + compatible =3D "allwinner,sun50i-r329-pinctrl"; > + reg =3D <0x02000400 0x400>; > + interrupts =3D , > + , > + , > + ; > + clocks =3D <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; > + clock-names =3D "apb", "hosc", "losc"; > + gpio-controller; > + #gpio-cells =3D <3>; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + > + uart0_pb_pins: uart0-pb-pins { > + pins =3D "PB4", "PB5"; > + function =3D "uart0"; > + }; > + > + mmc0_pf_pins: mmc0-pf-pins { > + pins =3D "PF0", "PF1", "PF2", > + "PF3", "PF4", "PF5"; > + function =3D "mmc0"; > + }; > + > + mmc1_clk_pg0: mmc1-clk-pg0 { > + pins =3D "PG0"; > + function =3D "mmc1_clk"; > + }; Argh, of course it was bound to happen :) Make sure your DT pass validation though, all your mmc1 node names will rep= ort errors. > + > + mmc1_cmd_pg1: mmc1-clk-pg1 { s/clk/cmd/ ? > + pins =3D "PG1"; > + function =3D "mmc1_cmd"; > + }; > + > + mmc1_d0_pg2: mmc1-clk-pg2 { s/clk/d0/ > + pins =3D "PG2"; > + function =3D "mmc1_d0"; > + }; > + > + mmc1_d1_pg3: mmc1-clk-pg3 { s/clk/d1/ > + pins =3D "PG3"; > + function =3D "mmc1_d1"; > + }; > + > + mmc1_d2_pg4: mmc1-clk-pg4 { s/clk/d2/ > + pins =3D "PG4"; > + function =3D "mmc1_d2"; > + }; > + > + mmc1_d3_pg5: mmc1-clk-pg5 { s/clk/d3/ > + pins =3D "PG5"; > + function =3D "mmc1_d3"; > + }; > + }; > + > + ccu: clock@2001000 { > + compatible =3D "allwinner,sun50i-r329-ccu"; > + reg =3D <0x02001000 0x1000>; > + clocks =3D <&osc24M>, <&rtc 0>, <&rtc 2>; > + clock-names =3D "hosc", "losc", "iosc"; Do we have a clock tree for the RTC? Is it the same than the H616? Maxime --dgafk337ems2a2tp Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYRzMcwAKCRDj7w1vZxhR xXubAQCzgwOn/xozaa+B1nNA1mS27othgAAj+ZYv8+zptsTnSgEAluhr8NOdrZ2p DpeJvbfAD8szA+MAucqVaH3TPgKtaAE= =bY26 -----END PGP SIGNATURE----- --dgafk337ems2a2tp--