From: Konrad Dybcio <konrad.dybcio@somainline.org>
To: ~postmarketos/upstreaming@lists.sr.ht
Cc: martin.botka@somainline.org,
angelogioacchino.delregno@somainline.org,
marijn.suijten@somainline.org, jamipkettunen@somainline.org,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 14/17] arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes
Date: Fri, 20 Aug 2021 22:49:23 +0200 [thread overview]
Message-ID: <20210820204926.235192-15-konrad.dybcio@somainline.org> (raw)
In-Reply-To: <20210820204926.235192-1-konrad.dybcio@somainline.org>
Add SDHCI1/2 nodes for eMMC and uSD card respectively.
Do note that most SM6350 devices seem to come with UFS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 81 ++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 9ca14fa8324a..df99d6207f1c 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -398,12 +399,92 @@ rng: rng@793000 {
clock-names = "core";
};
+ sdhc_1: sdhci@7c4000 {
+ compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x007c4000 0 0x1000>,
+ <0 0x007c5000 0 0x1000>,
+ <0 0x007c8000 0 0x8000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ qcom,dll-config = <0x000f642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd SM6350_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+ bus-width = <8>;
+ non-removable;
+ supports-cqe;
+
+ status = "disabled";
+
+ sdhc1_opp_table: sdhc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
#hwlock-cells = <1>;
};
+ sdhc_2: sdhci@8804000 {
+ compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd SM6350_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ bus-width = <4>;
+
+ status = "disabled";
+
+ sdhc2_opp_table: sdhc2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
reg = <0 0x088e3000 0 0x400>;
--
2.33.0
next prev parent reply other threads:[~2021-08-20 20:49 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
2021-08-20 20:49 ` [PATCH 01/17] dt-bindings: arm: cpus: Add Kryo 560 CPUs Konrad Dybcio
2021-08-24 16:46 ` Rob Herring
2021-08-20 20:49 ` [PATCH 02/17] arm64: dts: qcom: Add SM6350 device tree Konrad Dybcio
2021-08-21 14:55 ` Konrad Dybcio
2021-09-14 16:08 ` Bjorn Andersson
2021-08-20 20:49 ` [PATCH 03/17] arm64: dts: qcom: sm6350: Add LLCC node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 04/17] arm64: dts: qcom: sm6350: Add RPMHCC node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 05/17] arm64: dts: qcom: sm6350: Add GCC node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 06/17] arm64: dts: qcom: sm6350: Add TLMM block node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 07/17] arm64: dts: qcom: sm6350: Add USB1 nodes Konrad Dybcio
2021-08-20 20:49 ` [PATCH 08/17] arm64: dts: qcom: sm6350: Add cpufreq-hw support Konrad Dybcio
2021-08-20 20:49 ` [PATCH 09/17] arm64: dts: qcom: sm6350: Add TSENS nodes Konrad Dybcio
2021-08-20 20:49 ` [PATCH 10/17] arm64: dts: qcom: sm6350: Add AOSS_QMP Konrad Dybcio
2021-08-20 20:49 ` [PATCH 11/17] arm64: dts: qcom: sm6350: Add SPMI bus Konrad Dybcio
2021-08-20 20:49 ` [PATCH 12/17] arm64: dts: qcom: sm6350: Add PRNG node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 13/17] arm64: dts: qcom: sm6350: Add RPMHPD and BCM voter Konrad Dybcio
2021-08-20 20:49 ` Konrad Dybcio [this message]
2021-08-20 20:49 ` [PATCH 15/17] arm64: dts: qcom: sm6350: Add apps_smmu Konrad Dybcio
2021-08-20 20:49 ` [PATCH 16/17] arm64: dts: qcom: sm6350: Add iommus property to USB1 Konrad Dybcio
2021-08-20 20:49 ` [PATCH 17/17] arm64: dts: qcom: Add device tree for Sony Xperia 10 III Konrad Dybcio
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