From: "Pali Rohár" <pali@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh@kernel.org>
Cc: "Krzysztof Wilczyński" <kw@linux.com>,
"Marek Behún" <kabel@kernel.org>, "Marc Zyngier" <maz@kernel.org>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 2/3] PCI: aardvark: Fix masking MSI interrupts
Date: Mon, 23 Aug 2021 18:40:32 +0200 [thread overview]
Message-ID: <20210823164033.27491-3-pali@kernel.org> (raw)
In-Reply-To: <20210823164033.27491-1-pali@kernel.org>
Masking of individual MSI interrupts is done via PCIE_MSI_MASK_REG
register. At the driver probe time mask all MSI interrupts and then let
kernel IRQ chip code to unmask particular MSI interrupt when needed.
Signed-off-by: Pali Rohár <pali@kernel.org>
Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support")
---
Changes in v2:
* Guard register updates by raw spin lock
---
drivers/pci/controller/pci-aardvark.c | 52 ++++++++++++++++++++++++---
1 file changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 81c4a9ff91a3..0e81d7f37465 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -241,6 +241,7 @@ struct advk_pcie {
struct irq_domain *msi_inner_domain;
struct irq_chip msi_bottom_irq_chip;
struct irq_chip msi_irq_chip;
+ raw_spinlock_t msi_irq_lock;
struct msi_domain_info msi_domain_info;
DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
struct mutex msi_used_lock;
@@ -481,12 +482,10 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
- /* Disable All ISR0/1 Sources */
+ /* Disable All ISR0/1 and MSI Sources */
advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
-
- /* Unmask all MSIs */
- advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
/* Unmask summary MSI interrupt */
reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
@@ -1051,6 +1050,46 @@ static int advk_msi_set_affinity(struct irq_data *irq_data,
return -EINVAL;
}
+static void advk_msi_irq_mask(struct irq_data *d)
+{
+ struct advk_pcie *pcie = d->domain->host_data;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ unsigned long flags;
+ u32 mask;
+
+ raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
+ mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
+ mask |= BIT(hwirq);
+ advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
+ raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
+}
+
+static void advk_msi_irq_unmask(struct irq_data *d)
+{
+ struct advk_pcie *pcie = d->domain->host_data;
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ unsigned long flags;
+ u32 mask;
+
+ raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
+ mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
+ mask &= ~BIT(hwirq);
+ advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
+ raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
+}
+
+static void advk_msi_top_irq_mask(struct irq_data *d)
+{
+ pci_msi_mask_irq(d);
+ irq_chip_mask_parent(d);
+}
+
+static void advk_msi_top_irq_unmask(struct irq_data *d)
+{
+ pci_msi_unmask_irq(d);
+ irq_chip_unmask_parent(d);
+}
+
static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
unsigned int virq,
unsigned int nr_irqs, void *args)
@@ -1143,6 +1182,7 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
struct irq_chip *bottom_ic, *msi_ic;
struct msi_domain_info *msi_di;
+ raw_spin_lock_init(&pcie->msi_irq_lock);
mutex_init(&pcie->msi_used_lock);
bottom_ic = &pcie->msi_bottom_irq_chip;
@@ -1150,9 +1190,13 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
bottom_ic->name = "MSI";
bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
bottom_ic->irq_set_affinity = advk_msi_set_affinity;
+ bottom_ic->irq_mask = advk_msi_irq_mask;
+ bottom_ic->irq_unmask = advk_msi_irq_unmask;
msi_ic = &pcie->msi_irq_chip;
msi_ic->name = "advk-MSI";
+ msi_ic->irq_mask = advk_msi_top_irq_mask;
+ msi_ic->irq_unmask = advk_msi_top_irq_unmask;
msi_di = &pcie->msi_domain_info;
msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
--
2.20.1
next prev parent reply other threads:[~2021-08-23 16:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-15 10:36 [PATCH 0/3] PCI: aardvark: MSI interrupt fixes Pali Rohár
2021-08-15 10:36 ` [PATCH 1/3] PCI: aardvark: Fix reading MSI interrupt number Pali Rohár
2021-08-15 10:36 ` [PATCH 2/3] PCI: aardvark: Fix masking MSI interrupts Pali Rohár
2021-08-15 16:56 ` Marc Zyngier
2021-08-15 17:36 ` Pali Rohár
2021-08-15 21:55 ` Marc Zyngier
2021-08-15 23:10 ` Pali Rohár
2021-08-15 10:36 ` [PATCH 3/3] PCI: aardvark: Enable MSI-X support Pali Rohár
2021-08-23 16:40 ` [PATCH v2 0/3] PCI: aardvark: MSI interrupt fixes Pali Rohár
2021-08-23 16:40 ` [PATCH v2 1/3] PCI: aardvark: Fix reading MSI interrupt number Pali Rohár
2021-08-23 16:52 ` Marc Zyngier
2021-08-23 16:40 ` Pali Rohár [this message]
2021-08-23 16:40 ` [PATCH v2 3/3] PCI: aardvark: Enable MSI-X support Pali Rohár
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