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Wed, 25 Aug 2021 11:00:47 -0400 (EDT) Date: Wed, 25 Aug 2021 17:00:46 +0200 From: Maxime Ripard To: Samuel Holland Cc: Icenowy Zheng , Rob Herring , Chen-Yu Tsai , Jernej Skrabec , Ulf Hansson , Linus Walleij , Alexandre Belloni , Andre Przywara , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC Message-ID: <20210825150046.dpua45aeqrndxzbu@gilmour> References: <20210802062212.73220-1-icenowy@sipeed.com> <20210802062212.73220-16-icenowy@sipeed.com> <20210818090139.rllz4fvvq3pzdkls@gilmour> <74F51516-2470-4A49-972B-E19D8EDD9A3D@sipeed.com> <75ae9ef8-496b-68ca-214e-e8b270648a50@sholland.org> <8e4a49b8-8f17-d659-0952-0c96b0098139@sholland.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="qbmzml4ir2p77uxu" Content-Disposition: inline In-Reply-To: <8e4a49b8-8f17-d659-0952-0c96b0098139@sholland.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --qbmzml4ir2p77uxu Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Aug 19, 2021 at 10:06:43PM -0500, Samuel Holland wrote: > On 8/18/21 9:32 PM, Samuel Holland wrote: > > On 8/18/21 4:15 AM, Icenowy Zheng wrote: > >> =E4=BA=8E 2021=E5=B9=B48=E6=9C=8818=E6=97=A5 GMT+08:00 =E4=B8=8B=E5=8D= =885:01:39, Maxime Ripard =E5=86=99=E5=88=B0: > >>> On Mon, Aug 02, 2021 at 02:22:10PM +0800, Icenowy Zheng wrote: > >>>> + ccu: clock@2001000 { > >>>> + compatible =3D "allwinner,sun50i-r329-ccu"; > >>>> + reg =3D <0x02001000 0x1000>; > >>>> + clocks =3D <&osc24M>, <&rtc 0>, <&rtc 2>; > >>>> + clock-names =3D "hosc", "losc", "iosc"; > >>> > >>> Do we have a clock tree for the RTC? Is it the same than the H616? > >> > >> Nope, it's the same with H6 because of external LOSC crystal is > >> possible. (Although production M2A SoMs has it NC for cost control.) > >=20 > > It is not the same as the H6, either. The clock tree _is_ identical to = the D1, > > which has three diagrams on pages 363-364 of its user manual here: > >=20 > > https://dl.linux-sunxi.org/D1/D1_User_Manual_V0.1_Draft_Version.pdf > >=20 > > Compared to the H6, the R329/D1: > > - Loses the LOSC calibration circuit > > - Gains a third mux input for LOSC (not external 32k) to fanout > > - Gains a mux to choose between LOSC and HOSC/750 for the RTC clock > > - Gains an SPI bus clock input divided from the PRCM AHB > >=20 > > Compared to the H616, the R329/D1: > > - Has an external 32k crystal input > > - Gains the IOSC vs. external 32k crystal mux for LOSC > > - Switches fanout mux input #1 from pll_periph0/N to external 32k > > - Gains a mux to choose between LOSC and HOSC/750 for the RTC clock > > - Gains an SPI bus clock input divided from the PRCM AHB > >=20 > > So the R329/D1 RTC has three^Wfour inputs: > > - SPI clock from PRCM > > - 24 MHz DCXO crystal > > - 32 kHz external crystal (optional) >=20 > Whoops, I missed one here: > - Bus clock from PRCM >=20 > The SPI clock is new for R329, but the bus clock has been around since H6. >=20 > > and four outputs: > > - 16 MHz "IOSC" RC oscillator > > - 32 kHz "LOSC" > > - ~1 kHz for RTC timekeeping >=20 > Even though this is internal to the RTC, it is still useful to model, as = it can > be used to correct for known RTC drift. (For example, HOSC/750 is 32000 Hz > instead of 32768 Hz, so 2.34375% slow. But that is better than IOSC, whic= h has > unknown error.) If it's not useful to any other device, there's no real reason to model it in the clock framework. We should still force the source of the RTC to the most accurate option we have, but we can do that without the CCF. Maxime --qbmzml4ir2p77uxu Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYSZbHgAKCRDj7w1vZxhR xatPAP9SpY3ZG2Q2edvu8/rFpZAHUNCGGnz4rAG/qaugjp1l2AD8CnjkVWrr8xFL TtZt3w3Zrp8/E1OFyaW5O76k4StSzgo= =l0B8 -----END PGP SIGNATURE----- --qbmzml4ir2p77uxu--