From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 2/2] riscv: Move EXCEPTION_TABLE to RO_DATA segment
Date: Thu, 26 Aug 2021 22:11:18 +0800 [thread overview]
Message-ID: <20210826221118.24be1142@xhacker> (raw)
In-Reply-To: <20210826220952.77a68a9e@xhacker>
From: Jisheng Zhang <jszhang@kernel.org>
_ex_table section is read-only, so move it to RO_DATA.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/kernel/vmlinux-xip.lds.S | 1 -
arch/riscv/kernel/vmlinux.lds.S | 4 ++--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/vmlinux-xip.lds.S b/arch/riscv/kernel/vmlinux-xip.lds.S
index af776555ded9..9c9f35091ef0 100644
--- a/arch/riscv/kernel/vmlinux-xip.lds.S
+++ b/arch/riscv/kernel/vmlinux-xip.lds.S
@@ -121,7 +121,6 @@ SECTIONS
}
BSS_SECTION(PAGE_SIZE, PAGE_SIZE, 0)
- EXCEPTION_TABLE(0x10)
.rel.dyn : AT(ADDR(.rel.dyn) - LOAD_OFFSET) {
*(.rel.dyn*)
diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S
index 502d0826ecb1..5104f3a871e3 100644
--- a/arch/riscv/kernel/vmlinux.lds.S
+++ b/arch/riscv/kernel/vmlinux.lds.S
@@ -4,6 +4,8 @@
* Copyright (C) 2017 SiFive
*/
+#define RO_EXCEPTION_TABLE_ALIGN 16
+
#ifdef CONFIG_XIP_KERNEL
#include "vmlinux-xip.lds.S"
#else
@@ -112,8 +114,6 @@ SECTIONS
*(.srodata*)
}
- EXCEPTION_TABLE(0x10)
-
. = ALIGN(SECTION_ALIGN);
_data = .;
--
2.32.0
next prev parent reply other threads:[~2021-08-26 14:18 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-26 14:09 [PATCH v2 0/2] riscv: improve __ex_table section handling Jisheng Zhang
2021-08-26 14:10 ` [PATCH v2 1/2] riscv: Enable BUILDTIME_TABLE_SORT Jisheng Zhang
2021-08-26 14:11 ` Jisheng Zhang [this message]
2021-09-11 7:10 ` [PATCH v2 0/2] riscv: improve __ex_table section handling Palmer Dabbelt
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