* [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver
@ 2021-08-29 19:36 Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver Konrad Dybcio
` (8 more replies)
0 siblings, 9 replies; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:36 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Rob Herring, Andy Gross,
Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
Add documentation for the MSM8994 GCC driver.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Acked-by: Rob Herring <robh@kernel.org>
---
No changes since the original v2, only added Rob's A-b
.../bindings/clock/qcom,gcc-msm8994.yaml | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
new file mode 100644
index 000000000000..b44a844d894c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/qcom,gcc-msm8994.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Global Clock & Reset Controller Binding for MSM8994
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on MSM8994 and MSM8992.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-msm8994.h
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <tdas@codeaurora.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,gcc-msm8992
+ - qcom,gcc-msm8994
+
+ clocks:
+ items:
+ - description: XO source
+ - description: Sleep clock source
+
+ clock-names:
+ items:
+ - const: xo
+ - const: sleep
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ protected-clocks:
+ description:
+ Protected clock specifier list as per common clock binding.
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@300000 {
+ compatible = "qcom,gcc-msm8994";
+ reg = <0x300000 0x90000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&xo_board>, <&sleep_clk>;
+ clock-names = "xo", "sleep";
+ };
+...
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
@ 2021-08-29 19:36 ` Konrad Dybcio
2021-08-29 19:52 ` Stephen Boyd
2021-08-29 20:47 ` Dmitry Baryshkov
2021-08-29 19:36 ` [PATCH RESEND v2 3/9] clk: qcom: gcc-msm8994: Fix up SPI QUP clocks Konrad Dybcio
` (7 subsequent siblings)
8 siblings, 2 replies; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:36 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, linux-arm-msm, linux-clk,
linux-kernel
Switch to the newer-style parent_data and remove the hardcoded
xo clock.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/clk/qcom/gcc-msm8994.c | 860 ++++++++++++---------------------
1 file changed, 305 insertions(+), 555 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 144d2ba7a9be..8e9a8ebadf73 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -28,50 +28,17 @@ enum {
P_GPLL4,
};
-static const struct parent_map gcc_xo_gpll0_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
-};
-
-static const char * const gcc_xo_gpll0[] = {
- "xo",
- "gpll0",
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL4, 5 },
-};
-
-static const char * const gcc_xo_gpll0_gpll4[] = {
- "xo",
- "gpll0",
- "gpll4",
-};
-
-static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
- .hw.init = &(struct clk_init_data)
- {
- .name = "xo",
- .parent_names = (const char *[]) { "xo_board" },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-};
-
static struct clk_alpha_pll gpll0_early = {
- .offset = 0x00000,
+ .offset = 0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gpll0_early",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
@@ -79,10 +46,9 @@ static struct clk_alpha_pll gpll0_early = {
};
static struct clk_alpha_pll_postdiv gpll0 = {
- .offset = 0x00000,
+ .offset = 0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]) { "gpll0_early" },
.num_parents = 1,
@@ -96,10 +62,11 @@ static struct clk_alpha_pll gpll4_early = {
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gpll4_early",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
@@ -109,8 +76,7 @@ static struct clk_alpha_pll gpll4_early = {
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x1dc0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_names = (const char *[]) { "gpll4_early" },
.num_parents = 1,
@@ -118,6 +84,28 @@ static struct clk_alpha_pll_postdiv gpll4 = {
},
};
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0[] = {
+ { .fw_name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 5 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
+ { .fw_name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+};
+
static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
@@ -134,10 +122,9 @@ static struct clk_rcg2 ufs_axi_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_ufs_axi_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "ufs_axi_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -155,10 +142,9 @@ static struct clk_rcg2 usb30_master_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb30_master_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -175,10 +161,9 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -203,10 +188,9 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -217,10 +201,9 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -232,10 +215,9 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -246,10 +228,9 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -261,10 +242,9 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -275,10 +255,9 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -290,10 +269,9 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -304,10 +282,9 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -319,10 +296,9 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -333,10 +309,9 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -348,10 +323,9 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -382,10 +356,9 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -397,10 +370,9 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -412,10 +384,9 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -427,10 +398,9 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -442,10 +412,9 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -457,10 +426,9 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -471,10 +439,9 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -486,10 +453,9 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -500,10 +466,9 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -515,10 +480,9 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -529,10 +493,9 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -544,10 +507,9 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -558,10 +520,9 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -573,10 +534,9 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -587,10 +547,9 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -602,10 +561,9 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -616,10 +574,9 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -631,10 +588,9 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blspqup_spi_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -646,10 +602,9 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -661,10 +616,9 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -676,10 +630,9 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -691,10 +644,9 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -706,10 +658,9 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -721,10 +672,9 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_blsp_uart_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -743,10 +693,9 @@ static struct clk_rcg2 gp1_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gp1_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -765,10 +714,9 @@ static struct clk_rcg2 gp2_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gp2_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -787,10 +735,9 @@ static struct clk_rcg2 gp3_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_gp3_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -806,10 +753,11 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_pcie_0_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
@@ -824,10 +772,11 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
.cmd_rcgr = 0x1adc,
.hid_width = 5,
.freq_tbl = ftbl_pcie_pipe_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
@@ -843,10 +792,11 @@ static struct clk_rcg2 pcie_1_aux_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_pcie_1_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_aux_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
@@ -856,10 +806,11 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = {
.cmd_rcgr = 0x1b5c,
.hid_width = 5,
.freq_tbl = ftbl_pcie_pipe_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pcie_1_pipe_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
@@ -875,10 +826,9 @@ static struct clk_rcg2 pdm2_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_pdm2_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -902,10 +852,9 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_gpll4_map,
.freq_tbl = ftbl_sdcc1_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
+ .parent_data = gcc_xo_gpll0_gpll4,
.num_parents = 3,
.ops = &clk_rcg2_floor_ops,
},
@@ -928,10 +877,9 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_floor_ops,
},
@@ -943,10 +891,9 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc3_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_floor_ops,
},
@@ -958,10 +905,9 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_sdcc2_4_apps_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "sdcc4_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_floor_ops,
},
@@ -977,10 +923,11 @@ static struct clk_rcg2 tsif_ref_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.freq_tbl = ftbl_tsif_ref_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
@@ -997,10 +944,9 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -1015,10 +961,11 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
.cmd_rcgr = 0x1414,
.hid_width = 5,
.freq_tbl = ftbl_usb3_phy_aux_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
- .parent_names = (const char *[]) { "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ },
.num_parents = 1,
.ops = &clk_rcg2_ops,
},
@@ -1034,10 +981,9 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
.freq_tbl = ftbl_usb_hs_system_clk_src,
- .clkr.hw.init = &(struct clk_init_data)
- {
+ .clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = 2,
.ops = &clk_rcg2_ops,
},
@@ -1049,8 +995,7 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(17),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.ops = &clk_branch2_ops,
},
@@ -1062,12 +1007,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x0648,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup1_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1080,12 +1022,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.clkr = {
.enable_reg = 0x0644,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup1_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1098,12 +1037,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x06c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup2_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1116,12 +1052,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.clkr = {
.enable_reg = 0x06c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup2_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1134,12 +1067,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x0748,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup3_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1152,12 +1082,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.clkr = {
.enable_reg = 0x0744,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup3_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1170,12 +1097,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x07c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup4_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1188,12 +1112,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.clkr = {
.enable_reg = 0x07c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup4_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1206,12 +1127,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x0848,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup5_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1224,12 +1142,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.clkr = {
.enable_reg = 0x0844,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup5_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1242,12 +1157,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x08c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup6_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1260,12 +1172,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.clkr = {
.enable_reg = 0x08c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_qup6_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1278,12 +1187,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.clkr = {
.enable_reg = 0x0684,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart1_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1296,12 +1202,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.clkr = {
.enable_reg = 0x0704,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart2_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1314,12 +1217,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.clkr = {
.enable_reg = 0x0784,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart3_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1332,12 +1232,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
.clkr = {
.enable_reg = 0x0804,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart4_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1350,12 +1247,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
.clkr = {
.enable_reg = 0x0884,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart5_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1368,12 +1262,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
.clkr = {
.enable_reg = 0x0904,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
- .parent_names = (const char *[]) {
- "blsp1_uart6_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1387,8 +1278,7 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
.clkr = {
.enable_reg = 0x1484,
.enable_mask = BIT(15),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
.ops = &clk_branch2_ops,
},
@@ -1400,12 +1290,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x0988,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup1_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1418,12 +1305,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
.clkr = {
.enable_reg = 0x0984,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup1_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup1_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1436,12 +1320,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x0a08,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup2_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1454,12 +1335,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
.clkr = {
.enable_reg = 0x0a04,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup2_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup2_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1472,12 +1350,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x0a88,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup3_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1490,12 +1365,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
.clkr = {
.enable_reg = 0x0a84,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup3_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup3_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1508,12 +1380,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x0b08,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup4_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1526,12 +1395,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
.clkr = {
.enable_reg = 0x0b04,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup4_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup4_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1544,12 +1410,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x0b88,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup5_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1562,12 +1425,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
.clkr = {
.enable_reg = 0x0b84,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup5_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup5_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1580,12 +1440,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
.clkr = {
.enable_reg = 0x0c08,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_i2c_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup6_i2c_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1598,12 +1455,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
.clkr = {
.enable_reg = 0x0c04,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup6_spi_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_qup6_spi_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1616,12 +1470,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
.clkr = {
.enable_reg = 0x09c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart1_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart1_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1634,12 +1485,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
.clkr = {
.enable_reg = 0x0a44,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart2_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart2_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1652,12 +1500,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
.clkr = {
.enable_reg = 0x0ac4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart3_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart3_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1670,12 +1515,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
.clkr = {
.enable_reg = 0x0b44,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart4_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart4_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1688,12 +1530,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
.clkr = {
.enable_reg = 0x0bc4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart5_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart5_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1706,12 +1545,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
.clkr = {
.enable_reg = 0x0c44,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart6_apps_clk",
- .parent_names = (const char *[]) {
- "blsp2_uart6_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1724,12 +1560,9 @@ static struct clk_branch gcc_gp1_clk = {
.clkr = {
.enable_reg = 0x1900,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
- .parent_names = (const char *[]) {
- "gp1_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1742,12 +1575,9 @@ static struct clk_branch gcc_gp2_clk = {
.clkr = {
.enable_reg = 0x1940,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
- .parent_names = (const char *[]) {
- "gp2_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1760,12 +1590,9 @@ static struct clk_branch gcc_gp3_clk = {
.clkr = {
.enable_reg = 0x1980,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
- .parent_names = (const char *[]) {
- "gp3_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1778,8 +1605,7 @@ static struct clk_branch gcc_lpass_q6_axi_clk = {
.clkr = {
.enable_reg = 0x0280,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_axi_clk",
.ops = &clk_branch2_ops,
},
@@ -1791,8 +1617,7 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.clkr = {
.enable_reg = 0x0284,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
.ops = &clk_branch2_ops,
},
@@ -1804,12 +1629,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
.clkr = {
.enable_reg = 0x1ad4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
- .parent_names = (const char *[]) {
- "pcie_0_aux_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1822,8 +1644,7 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.clkr = {
.enable_reg = 0x1ad0,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
@@ -1835,8 +1656,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.clkr = {
.enable_reg = 0x1acc,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
@@ -1849,12 +1669,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
.clkr = {
.enable_reg = 0x1ad8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
- .parent_names = (const char *[]) {
- "pcie_0_pipe_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1868,8 +1685,7 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.clkr = {
.enable_reg = 0x1ac8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
@@ -1881,12 +1697,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
.clkr = {
.enable_reg = 0x1b54,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk",
- .parent_names = (const char *[]) {
- "pcie_1_aux_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1899,8 +1712,7 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.clkr = {
.enable_reg = 0x1b54,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
@@ -1912,8 +1724,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.clkr = {
.enable_reg = 0x1b50,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
@@ -1926,12 +1737,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
.clkr = {
.enable_reg = 0x1b58,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk",
- .parent_names = (const char *[]) {
- "pcie_1_pipe_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1944,8 +1752,7 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.clkr = {
.enable_reg = 0x1b48,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
@@ -1957,12 +1764,9 @@ static struct clk_branch gcc_pdm2_clk = {
.clkr = {
.enable_reg = 0x0ccc,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
- .parent_names = (const char *[]) {
- "pdm2_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1975,8 +1779,7 @@ static struct clk_branch gcc_pdm_ahb_clk = {
.clkr = {
.enable_reg = 0x0cc4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
@@ -1988,12 +1791,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
.clkr = {
.enable_reg = 0x04c4,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
- .parent_names = (const char *[]) {
- "sdcc1_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2006,8 +1806,7 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
.clkr = {
.enable_reg = 0x04c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.parent_names = (const char *[]){
"periph_noc_clk_src",
@@ -2023,8 +1822,7 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
.clkr = {
.enable_reg = 0x0508,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.parent_names = (const char *[]){
"periph_noc_clk_src",
@@ -2040,12 +1838,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.clkr = {
.enable_reg = 0x0504,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
- .parent_names = (const char *[]) {
- "sdcc2_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2058,8 +1853,7 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
.clkr = {
.enable_reg = 0x0548,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_ahb_clk",
.parent_names = (const char *[]){
"periph_noc_clk_src",
@@ -2075,12 +1869,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
.clkr = {
.enable_reg = 0x0544,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_apps_clk",
- .parent_names = (const char *[]) {
- "sdcc3_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2093,8 +1884,7 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
.clkr = {
.enable_reg = 0x0588,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
.parent_names = (const char *[]){
"periph_noc_clk_src",
@@ -2110,12 +1900,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
.clkr = {
.enable_reg = 0x0584,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk",
- .parent_names = (const char *[]) {
- "sdcc4_apps_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2128,12 +1915,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
.clkr = {
.enable_reg = 0x1d7c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_axi_clk",
- .parent_names = (const char *[]) {
- "ufs_axi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2146,12 +1930,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
.clkr = {
.enable_reg = 0x03fc,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_axi_clk",
- .parent_names = (const char *[]) {
- "usb30_master_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2164,8 +1945,7 @@ static struct clk_branch gcc_tsif_ahb_clk = {
.clkr = {
.enable_reg = 0x0d84,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
.ops = &clk_branch2_ops,
},
@@ -2177,12 +1957,9 @@ static struct clk_branch gcc_tsif_ref_clk = {
.clkr = {
.enable_reg = 0x0d88,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk",
- .parent_names = (const char *[]) {
- "tsif_ref_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2195,8 +1972,7 @@ static struct clk_branch gcc_ufs_ahb_clk = {
.clkr = {
.enable_reg = 0x1d4c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
.ops = &clk_branch2_ops,
},
@@ -2208,12 +1984,9 @@ static struct clk_branch gcc_ufs_axi_clk = {
.clkr = {
.enable_reg = 0x1d48,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_axi_clk",
- .parent_names = (const char *[]) {
- "ufs_axi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2226,12 +1999,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
.clkr = {
.enable_reg = 0x1d54,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_cfg_clk",
- .parent_names = (const char *[]) {
- "ufs_axi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2245,8 +2015,7 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
.clkr = {
.enable_reg = 0x1d60,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
@@ -2259,8 +2028,7 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
.clkr = {
.enable_reg = 0x1d64,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
@@ -2272,12 +2040,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
.clkr = {
.enable_reg = 0x1d50,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_cfg_clk",
- .parent_names = (const char *[]) {
- "ufs_axi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2291,8 +2056,7 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
.clkr = {
.enable_reg = 0x1d58,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_0_clk",
.ops = &clk_branch2_ops,
},
@@ -2305,8 +2069,7 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
.clkr = {
.enable_reg = 0x1d5c,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_1_clk",
.ops = &clk_branch2_ops,
},
@@ -2318,9 +2081,13 @@ static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
.clkr = {
.enable_reg = 0x04ac,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb2_hs_phy_sleep_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep",
+ .name = "sleep"
+ },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -2331,12 +2098,9 @@ static struct clk_branch gcc_usb30_master_clk = {
.clkr = {
.enable_reg = 0x03c8,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
- .parent_names = (const char *[]) {
- "usb30_master_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2349,12 +2113,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
.clkr = {
.enable_reg = 0x03d0,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
- .parent_names = (const char *[]) {
- "usb30_mock_utmi_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2367,9 +2128,13 @@ static struct clk_branch gcc_usb30_sleep_clk = {
.clkr = {
.enable_reg = 0x03cc,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sleep_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep",
+ .name = "sleep"
+ },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -2380,12 +2145,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
.clkr = {
.enable_reg = 0x1408,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
- .parent_names = (const char *[]) {
- "usb3_phy_aux_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2398,8 +2160,7 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
.clkr = {
.enable_reg = 0x0488,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
.ops = &clk_branch2_ops,
},
@@ -2411,12 +2172,9 @@ static struct clk_branch gcc_usb_hs_system_clk = {
.clkr = {
.enable_reg = 0x0484,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
- .parent_names = (const char *[]) {
- "usb_hs_system_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2429,8 +2187,7 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.clkr = {
.enable_reg = 0x1a84,
.enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data)
- {
+ .hw.init = &(struct clk_init_data){
.name = "gcc_usb_phy_cfg_ahb2phy_clk",
.ops = &clk_branch2_ops,
},
@@ -2663,13 +2420,6 @@ MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
static int gcc_msm8994_probe(struct platform_device *pdev)
{
- struct device *dev = &pdev->dev;
- struct clk *clk;
-
- clk = devm_clk_register(dev, &xo.hw);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
return qcom_cc_probe(pdev, &gcc_msm8994_desc);
}
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH RESEND v2 3/9] clk: qcom: gcc-msm8994: Fix up SPI QUP clocks
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver Konrad Dybcio
@ 2021-08-29 19:36 ` Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 4/9] clk: qcom: gcc-msm8994: Add missing NoC clocks Konrad Dybcio
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:36 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, linux-arm-msm, linux-clk,
linux-kernel
Fix up SPI QUP freq tables to account for the fact
that not every QUP can run at the same set of frequencies.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/clk/qcom/gcc-msm8994.c | 118 +++++++++++++++++++++++++++++----
1 file changed, 105 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 8e9a8ebadf73..78c06104854e 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -169,7 +169,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
},
};
-static struct freq_tbl ftbl_blspqup_spi_apps_clk_src[] = {
+static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
F(960000, P_XO, 10, 1, 2),
F(4800000, P_XO, 4, 0, 0),
F(9600000, P_XO, 2, 0, 0),
@@ -187,7 +187,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -209,12 +209,25 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
},
};
+static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(46150000, P_GPLL0, 13, 0, 0),
+ { }
+};
+
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.cmd_rcgr = 0x06cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -236,12 +249,25 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
},
};
+static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(44440000, P_GPLL0, 13.5, 0, 0),
+ { }
+};
+
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.cmd_rcgr = 0x074c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -268,7 +294,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -290,12 +316,25 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
},
};
+static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(40000000, P_GPLL0, 15, 0, 0),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ { }
+};
+
static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.cmd_rcgr = 0x084c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -317,12 +356,25 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
},
};
+static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(27906976, P_GPLL0, 1, 2, 43),
+ F(41380000, P_GPLL0, 15, 0, 0),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ { }
+};
+
static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x08cc,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -447,12 +499,25 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
},
};
+static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(44440000, P_GPLL0, 13.5, 0, 0),
+ { }
+};
+
static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x098c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup1_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -479,7 +544,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup2_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -488,6 +553,19 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
},
};
+static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(42860000, P_GPLL0, 14, 0, 0),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ { }
+};
+
static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
.cmd_rcgr = 0x0aa0,
.hid_width = 5,
@@ -506,7 +584,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup3_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -533,7 +611,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup4_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -560,7 +638,8 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup5_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
@@ -582,12 +661,25 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
},
};
+static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 12.5, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(44440000, P_GPLL0, 13.5, 0, 0),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ { }
+};
+
static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
.cmd_rcgr = 0x0c0c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll0_map,
- .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
+ .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup6_spi_apps_clk_src",
.parent_data = gcc_xo_gpll0,
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH RESEND v2 4/9] clk: qcom: gcc-msm8994: Add missing NoC clocks
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 3/9] clk: qcom: gcc-msm8994: Fix up SPI QUP clocks Konrad Dybcio
@ 2021-08-29 19:36 ` Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 5/9] clk: qcom: gcc-msm8994: Add missing clocks Konrad Dybcio
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:36 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring, linux-arm-msm,
linux-clk, linux-kernel, devicetree
Add necessary NoC clocks to provide frequency sources for
relevant branch clocks.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/clk/qcom/gcc-msm8994.c | 101 ++++++++++++++++---
include/dt-bindings/clock/qcom,gcc-msm8994.h | 3 +
2 files changed, 92 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 78c06104854e..629ab6ab455f 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -106,6 +106,42 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
{ .hw = &gpll4.clkr.hw },
};
+static struct clk_rcg2 system_noc_clk_src = {
+ .cmd_rcgr = 0x0120,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "system_noc_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 config_noc_clk_src = {
+ .cmd_rcgr = 0x0150,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "config_noc_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 periph_noc_clk_src = {
+ .cmd_rcgr = 0x0190,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "periph_noc_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
@@ -1089,6 +1125,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
.enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -1372,6 +1410,8 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -1699,6 +1739,8 @@ static struct clk_branch gcc_lpass_q6_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_lpass_q6_axi_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -1711,6 +1753,8 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -1738,6 +1782,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_cfg_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1750,6 +1797,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_mstr_axi_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1779,6 +1829,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_slv_axi_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1806,6 +1859,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_cfg_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1818,6 +1874,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_mstr_axi_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1846,6 +1905,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_slv_axi_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1873,6 +1935,8 @@ static struct clk_branch gcc_pdm_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -1900,10 +1964,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
.num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1916,10 +1979,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
.num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1947,10 +2009,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc3_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
.num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -1978,10 +2039,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_ahb_clk",
- .parent_names = (const char *[]){
- "periph_noc_clk_src",
- },
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
.num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -2039,6 +2099,8 @@ static struct clk_branch gcc_tsif_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -2066,6 +2128,8 @@ static struct clk_branch gcc_ufs_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -2109,6 +2173,8 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_0_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -2122,6 +2188,8 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_rx_symbol_1_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -2150,6 +2218,8 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_0_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -2163,6 +2233,8 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_tx_symbol_1_clk",
+ .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -2254,6 +2326,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -2331,6 +2405,9 @@ static struct clk_regmap *gcc_msm8994_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL4_EARLY] = &gpll4_early.clkr,
[GPLL4] = &gpll4.clkr,
+ [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
+ [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
+ [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
[UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h
index 507b8d6effd2..219d5441c0fa 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8994.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h
@@ -148,6 +148,9 @@
#define GCC_USB30_SLEEP_CLK 138
#define GCC_USB_HS_AHB_CLK 139
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 140
+#define CONFIG_NOC_CLK_SRC 141
+#define PERIPH_NOC_CLK_SRC 142
+#define SYSTEM_NOC_CLK_SRC 143
/* GDSCs */
#define PCIE_GDSC 0
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH RESEND v2 5/9] clk: qcom: gcc-msm8994: Add missing clocks
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
` (2 preceding siblings ...)
2021-08-29 19:36 ` [PATCH RESEND v2 4/9] clk: qcom: gcc-msm8994: Add missing NoC clocks Konrad Dybcio
@ 2021-08-29 19:36 ` Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 6/9] clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE Konrad Dybcio
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:36 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring, linux-arm-msm,
linux-clk, linux-kernel, devicetree
This should be the last "add missing clocks" commit, as to
my knowledge there are no more clocks registered within gcc.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/clk/qcom/gcc-msm8994.c | 134 +++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-msm8994.h | 9 ++
2 files changed, 143 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 629ab6ab455f..98b2fd429629 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -2319,6 +2319,19 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
},
};
+static struct clk_branch gcc_usb3_phy_pipe_clk = {
+ .halt_reg = 0x140c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x140c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_usb_hs_ahb_clk = {
.halt_reg = 0x0488,
.clkr = {
@@ -2360,6 +2373,118 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
},
};
+static struct clk_branch gpll0_out_mmsscc = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1484,
+ .enable_mask = BIT(26),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_out_mmsscc",
+ .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpll0_out_msscc = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1484,
+ .enable_mask = BIT(27),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_out_msscc",
+ .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch pcie_0_phy_ldo = {
+ .halt_reg = 0x1e00,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x1E00,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_0_phy_ldo",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch pcie_1_phy_ldo = {
+ .halt_reg = 0x1e04,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x1E04,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie_1_phy_ldo",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch ufs_phy_ldo = {
+ .halt_reg = 0x1e0c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x1E0C,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "ufs_phy_ldo",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch usb_ss_phy_ldo = {
+ .halt_reg = 0x1e08,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x1E08,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "usb_ss_phy_ldo",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x0e04,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x0e04,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1484,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_boot_rom_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x0d04,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1484,
+ .enable_mask = BIT(13),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct gdsc pcie_gdsc = {
.gdscr = 0x1e18,
.pd = {
@@ -2542,9 +2667,18 @@ static struct clk_regmap *gcc_msm8994_clocks[] = {
[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+ [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+ [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr,
+ [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
+ [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr,
+ [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr,
+ [UFS_PHY_LDO] = &ufs_phy_ldo.clkr,
+ [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
};
static struct gdsc *gcc_msm8994_gdscs[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h
index 219d5441c0fa..dcb49817dcec 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8994.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h
@@ -151,6 +151,15 @@
#define CONFIG_NOC_CLK_SRC 141
#define PERIPH_NOC_CLK_SRC 142
#define SYSTEM_NOC_CLK_SRC 143
+#define GPLL0_OUT_MMSSCC 144
+#define GPLL0_OUT_MSSCC 145
+#define PCIE_0_PHY_LDO 146
+#define PCIE_1_PHY_LDO 147
+#define UFS_PHY_LDO 148
+#define USB_SS_PHY_LDO 149
+#define GCC_BOOT_ROM_AHB_CLK 150
+#define GCC_PRNG_AHB_CLK 151
+#define GCC_USB3_PHY_PIPE_CLK 152
/* GDSCs */
#define PCIE_GDSC 0
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH RESEND v2 6/9] clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
` (3 preceding siblings ...)
2021-08-29 19:36 ` [PATCH RESEND v2 5/9] clk: qcom: gcc-msm8994: Add missing clocks Konrad Dybcio
@ 2021-08-29 19:36 ` Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 7/9] clk: qcom: gcc-msm8994: Add modem reset Konrad Dybcio
` (3 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:36 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, linux-arm-msm, linux-clk,
linux-kernel
This GDSC is not present on msm8994.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/clk/qcom/gcc-msm8994.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 98b2fd429629..2ed206ecb60d 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -2485,14 +2485,6 @@ static struct clk_branch gcc_prng_ahb_clk = {
},
};
-static struct gdsc pcie_gdsc = {
- .gdscr = 0x1e18,
- .pd = {
- .name = "pcie",
- },
- .pwrsts = PWRSTS_OFF_ON,
-};
-
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x1ac4,
.pd = {
@@ -2682,7 +2674,8 @@ static struct clk_regmap *gcc_msm8994_clocks[] = {
};
static struct gdsc *gcc_msm8994_gdscs[] = {
- [PCIE_GDSC] = &pcie_gdsc,
+ /* This GDSC does not exist, but ABI has to remain intact */
+ [PCIE_GDSC] = NULL,
[PCIE_0_GDSC] = &pcie_0_gdsc,
[PCIE_1_GDSC] = &pcie_1_gdsc,
[USB30_GDSC] = &usb30_gdsc,
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH RESEND v2 7/9] clk: qcom: gcc-msm8994: Add modem reset
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
` (4 preceding siblings ...)
2021-08-29 19:36 ` [PATCH RESEND v2 6/9] clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE Konrad Dybcio
@ 2021-08-29 19:36 ` Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 8/9] clk: qcom: gcc-msm8994: Add proper msm8992 support Konrad Dybcio
` (2 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:36 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring, linux-arm-msm,
linux-clk, linux-kernel, devicetree
This will be required to support the modem.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/clk/qcom/gcc-msm8994.c | 1 +
include/dt-bindings/clock/qcom,gcc-msm8994.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 2ed206ecb60d..7545e973fd0d 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -2685,6 +2685,7 @@ static struct gdsc *gcc_msm8994_gdscs[] = {
static const struct qcom_reset_map gcc_msm8994_resets[] = {
[USB3_PHY_RESET] = { 0x1400 },
[USB3PHY_PHY_RESET] = { 0x1404 },
+ [MSS_RESET] = { 0x1680 },
[PCIE_PHY_0_RESET] = { 0x1b18 },
[PCIE_PHY_1_RESET] = { 0x1b98 },
[QUSB2_PHY_RESET] = { 0x04b8 },
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h
index dcb49817dcec..f6836f430bb5 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8994.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h
@@ -174,5 +174,6 @@
#define PCIE_PHY_0_RESET 2
#define PCIE_PHY_1_RESET 3
#define QUSB2_PHY_RESET 4
+#define MSS_RESET 5
#endif
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH RESEND v2 8/9] clk: qcom: gcc-msm8994: Add proper msm8992 support
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
` (5 preceding siblings ...)
2021-08-29 19:36 ` [PATCH RESEND v2 7/9] clk: qcom: gcc-msm8994: Add modem reset Konrad Dybcio
@ 2021-08-29 19:36 ` Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 9/9] clk: qcom: gcc-msm8994: Add a quirk for a different SDCC configuration Konrad Dybcio
2021-08-30 11:49 ` [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Rob Herring
8 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:36 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, linux-arm-msm, linux-clk,
linux-kernel
MSM8992 is a cut-down version of MSM8994, featuring
largely the same hardware.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/clk/qcom/gcc-msm8994.c | 73 +++++++++++++++++++++++++++++++++-
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 7545e973fd0d..72038e4c04df 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -8,6 +8,7 @@
#include <linux/ctype.h>
#include <linux/io.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/regmap.h>
@@ -218,6 +219,17 @@ static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
{ }
};
+static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.cmd_rcgr = 0x064c,
.mnd_width = 8,
@@ -974,6 +986,18 @@ static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
{ }
};
+static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0, 15, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(172000000, P_GPLL4, 2, 0, 0),
+ F(344000000, P_GPLL4, 1, 0, 0),
+ { }
+};
+
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x04d0,
.mnd_width = 8,
@@ -2710,13 +2734,60 @@ static const struct qcom_cc_desc gcc_msm8994_desc = {
};
static const struct of_device_id gcc_msm8994_match_table[] = {
- { .compatible = "qcom,gcc-msm8994" },
+ { .compatible = "qcom,gcc-msm8992" },
+ { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */
{}
};
MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
static int gcc_msm8994_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
+
+ if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) {
+ /* MSM8992 features less clocks and some have different freq tables */
+ gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL;
+ gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL;
+ gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL;
+ gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL;
+
+ sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992;
+ blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+ blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
+
+ /*
+ * Some 8992 boards might *possibly* use
+ * PCIe1 clocks and controller, but it's not
+ * standard and they should be disabled otherwise.
+ */
+ gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL;
+ gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL;
+ gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL;
+ gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL;
+ gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
+ }
+
return qcom_cc_probe(pdev, &gcc_msm8994_desc);
}
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH RESEND v2 9/9] clk: qcom: gcc-msm8994: Add a quirk for a different SDCC configuration
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
` (6 preceding siblings ...)
2021-08-29 19:36 ` [PATCH RESEND v2 8/9] clk: qcom: gcc-msm8994: Add proper msm8992 support Konrad Dybcio
@ 2021-08-29 19:36 ` Konrad Dybcio
2021-08-29 19:50 ` Stephen Boyd
2021-08-30 11:49 ` [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Rob Herring
8 siblings, 1 reply; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:36 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring, Taniya Das,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Some devices come with a different SDCC clock configuration,
account for that.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
.../bindings/clock/qcom,gcc-msm8994.yaml | 4 ++++
drivers/clk/qcom/gcc-msm8994.c | 16 ++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
index b44a844d894c..4ba2f72d3cad 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
@@ -49,6 +49,10 @@ properties:
description:
Protected clock specifier list as per common clock binding.
+ qcom,sdcc2-clk-src-40mhz:
+ description: SDCC2_APPS clock source runs at 40MHz.
+ type: boolean
+
required:
- compatible
- reg
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 72038e4c04df..55c0fd069640 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -1012,6 +1012,19 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
},
};
+static struct freq_tbl ftbl_sdcc2_40mhz_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0, 15, 1, 2),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(40000000, P_GPLL0, 15, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ F(80000000, P_GPLL0, 7.5, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
F(144000, P_XO, 16, 3, 25),
F(400000, P_XO, 12, 1, 4),
@@ -2788,6 +2801,9 @@ static int gcc_msm8994_probe(struct platform_device *pdev)
gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
}
+ if (of_find_property(dev->of_node, "qcom,sdcc2-clk-src-40mhz", NULL))
+ sdcc2_apps_clk_src.freq_tbl = ftbl_sdcc2_40mhz_apps_clk_src;
+
return qcom_cc_probe(pdev, &gcc_msm8994_desc);
}
--
2.33.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH RESEND v2 9/9] clk: qcom: gcc-msm8994: Add a quirk for a different SDCC configuration
2021-08-29 19:36 ` [PATCH RESEND v2 9/9] clk: qcom: gcc-msm8994: Add a quirk for a different SDCC configuration Konrad Dybcio
@ 2021-08-29 19:50 ` Stephen Boyd
0 siblings, 0 replies; 14+ messages in thread
From: Stephen Boyd @ 2021-08-29 19:50 UTC (permalink / raw)
To: Konrad Dybcio, ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, Rob Herring, Taniya Das, linux-arm-msm,
linux-clk, devicetree, linux-kernel
Quoting Konrad Dybcio (2021-08-29 12:36:16)
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
> index b44a844d894c..4ba2f72d3cad 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
> @@ -49,6 +49,10 @@ properties:
> description:
> Protected clock specifier list as per common clock binding.
>
> + qcom,sdcc2-clk-src-40mhz:
> + description: SDCC2_APPS clock source runs at 40MHz.
> + type: boolean
> +
> required:
> - compatible
> - reg
> diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
> index 72038e4c04df..55c0fd069640 100644
> --- a/drivers/clk/qcom/gcc-msm8994.c
> +++ b/drivers/clk/qcom/gcc-msm8994.c
> @@ -1012,6 +1012,19 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
> },
> };
>
> +static struct freq_tbl ftbl_sdcc2_40mhz_apps_clk_src[] = {
> + F(144000, P_XO, 16, 3, 25),
> + F(400000, P_XO, 12, 1, 4),
> + F(20000000, P_GPLL0, 15, 1, 2),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(40000000, P_GPLL0, 15, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + F(80000000, P_GPLL0, 7.5, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
It should work to add more frequencies to the existing table. The
consumer will need to pick the correct frequency. That can be achieved
with an OPP table if necessary, in the consumer node.
> + { }
> +};
> +
> static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
> F(144000, P_XO, 16, 3, 25),
> F(400000, P_XO, 12, 1, 4),
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver
2021-08-29 19:36 ` [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver Konrad Dybcio
@ 2021-08-29 19:52 ` Stephen Boyd
2021-08-29 19:55 ` Konrad Dybcio
2021-08-29 20:47 ` Dmitry Baryshkov
1 sibling, 1 reply; 14+ messages in thread
From: Stephen Boyd @ 2021-08-29 19:52 UTC (permalink / raw)
To: Konrad Dybcio, ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Michael Turquette, linux-arm-msm, linux-clk, linux-kernel
Quoting Konrad Dybcio (2021-08-29 12:36:09)
> Switch to the newer-style parent_data and remove the hardcoded
> xo clock.
This is OK because nothing else is using the hardcoded name of "xo",
like another clk driver on this SoC?
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver
2021-08-29 19:52 ` Stephen Boyd
@ 2021-08-29 19:55 ` Konrad Dybcio
0 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2021-08-29 19:55 UTC (permalink / raw)
To: Stephen Boyd, ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Andy Gross, Bjorn Andersson, Michael Turquette,
linux-arm-msm, linux-clk, linux-kernel
On 29.08.2021 21:52, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2021-08-29 12:36:09)
>> Switch to the newer-style parent_data and remove the hardcoded
>> xo clock.
> This is OK because nothing else is using the hardcoded name of "xo",
> like another clk driver on this SoC?
8994 only has RPMCC and MMCC* apart from GCC and both are prepared for this.
*not counting DEBUGCC and CPUCC for obvious reasons (they are missing upstream)
Konrad
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver
2021-08-29 19:36 ` [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver Konrad Dybcio
2021-08-29 19:52 ` Stephen Boyd
@ 2021-08-29 20:47 ` Dmitry Baryshkov
1 sibling, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2021-08-29 20:47 UTC (permalink / raw)
To: Konrad Dybcio
Cc: ~postmarketos/upstreaming, Martin Botka,
AngeloGioacchino Del Regno, Marijn Suijten, jamipkettunen,
Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
open list:DRM DRIVER FOR MSM ADRENO GPU,
open list:COMMON CLK FRAMEWORK, open list
On Sun, 29 Aug 2021 at 22:36, Konrad Dybcio
<konrad.dybcio@somainline.org> wrote:
>
> Switch to the newer-style parent_data and remove the hardcoded
> xo clock.
As you are switching this to parent_data, it might be a good idea to
switch num_parents to ARRAY_SIZE instead of hardcoding a size of
arrays (for the cases where the array is not defined in the clock
definition itself).
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
> drivers/clk/qcom/gcc-msm8994.c | 860 ++++++++++++---------------------
> 1 file changed, 305 insertions(+), 555 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
> index 144d2ba7a9be..8e9a8ebadf73 100644
> --- a/drivers/clk/qcom/gcc-msm8994.c
> +++ b/drivers/clk/qcom/gcc-msm8994.c
> @@ -28,50 +28,17 @@ enum {
> P_GPLL4,
> };
>
> -static const struct parent_map gcc_xo_gpll0_map[] = {
> - { P_XO, 0 },
> - { P_GPLL0, 1 },
> -};
> -
> -static const char * const gcc_xo_gpll0[] = {
> - "xo",
> - "gpll0",
> -};
> -
> -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> - { P_XO, 0 },
> - { P_GPLL0, 1 },
> - { P_GPLL4, 5 },
> -};
> -
> -static const char * const gcc_xo_gpll0_gpll4[] = {
> - "xo",
> - "gpll0",
> - "gpll4",
> -};
> -
> -static struct clk_fixed_factor xo = {
> - .mult = 1,
> - .div = 1,
> - .hw.init = &(struct clk_init_data)
> - {
> - .name = "xo",
> - .parent_names = (const char *[]) { "xo_board" },
> - .num_parents = 1,
> - .ops = &clk_fixed_factor_ops,
> - },
> -};
> -
> static struct clk_alpha_pll gpll0_early = {
> - .offset = 0x00000,
> + .offset = 0,
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> .clkr = {
> .enable_reg = 0x1480,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gpll0_early",
> - .parent_names = (const char *[]) { "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo",
> + },
> .num_parents = 1,
> .ops = &clk_alpha_pll_ops,
> },
> @@ -79,10 +46,9 @@ static struct clk_alpha_pll gpll0_early = {
> };
>
> static struct clk_alpha_pll_postdiv gpll0 = {
> - .offset = 0x00000,
> + .offset = 0,
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "gpll0",
> .parent_names = (const char *[]) { "gpll0_early" },
> .num_parents = 1,
> @@ -96,10 +62,11 @@ static struct clk_alpha_pll gpll4_early = {
> .clkr = {
> .enable_reg = 0x1480,
> .enable_mask = BIT(4),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gpll4_early",
> - .parent_names = (const char *[]) { "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo",
> + },
> .num_parents = 1,
> .ops = &clk_alpha_pll_ops,
> },
> @@ -109,8 +76,7 @@ static struct clk_alpha_pll gpll4_early = {
> static struct clk_alpha_pll_postdiv gpll4 = {
> .offset = 0x1dc0,
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "gpll4",
> .parent_names = (const char *[]) { "gpll4_early" },
> .num_parents = 1,
> @@ -118,6 +84,28 @@ static struct clk_alpha_pll_postdiv gpll4 = {
> },
> };
>
> +static const struct parent_map gcc_xo_gpll0_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0[] = {
> + { .fw_name = "xo" },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL4, 5 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> + { .fw_name = "xo" },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll4.clkr.hw },
> +};
> +
> static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
> F(50000000, P_GPLL0, 12, 0, 0),
> F(100000000, P_GPLL0, 6, 0, 0),
> @@ -134,10 +122,9 @@ static struct clk_rcg2 ufs_axi_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_ufs_axi_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "ufs_axi_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -155,10 +142,9 @@ static struct clk_rcg2 usb30_master_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_usb30_master_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "usb30_master_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -175,10 +161,9 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -203,10 +188,9 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -217,10 +201,9 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -232,10 +215,9 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -246,10 +228,9 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -261,10 +242,9 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -275,10 +255,9 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -290,10 +269,9 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -304,10 +282,9 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -319,10 +296,9 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -333,10 +309,9 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -348,10 +323,9 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -382,10 +356,9 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart1_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -397,10 +370,9 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart2_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -412,10 +384,9 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart3_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -427,10 +398,9 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart4_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -442,10 +412,9 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart5_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -457,10 +426,9 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart6_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -471,10 +439,9 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup1_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -486,10 +453,9 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup1_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -500,10 +466,9 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup2_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -515,10 +480,9 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup2_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -529,10 +493,9 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup3_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -544,10 +507,9 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup3_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -558,10 +520,9 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup4_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -573,10 +534,9 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup4_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -587,10 +547,9 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup5_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -602,10 +561,9 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup5_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -616,10 +574,9 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup6_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -631,10 +588,9 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blspqup_spi_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_qup6_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -646,10 +602,9 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart1_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -661,10 +616,9 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart2_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -676,10 +630,9 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart3_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -691,10 +644,9 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart4_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -706,10 +658,9 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart5_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -721,10 +672,9 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp2_uart6_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -743,10 +693,9 @@ static struct clk_rcg2 gp1_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_gp1_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "gp1_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -765,10 +714,9 @@ static struct clk_rcg2 gp2_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_gp2_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "gp2_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -787,10 +735,9 @@ static struct clk_rcg2 gp3_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_gp3_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "gp3_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -806,10 +753,11 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
> .mnd_width = 8,
> .hid_width = 5,
> .freq_tbl = ftbl_pcie_0_aux_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_0_aux_clk_src",
> - .parent_names = (const char *[]) { "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo",
> + },
> .num_parents = 1,
> .ops = &clk_rcg2_ops,
> },
> @@ -824,10 +772,11 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
> .cmd_rcgr = 0x1adc,
> .hid_width = 5,
> .freq_tbl = ftbl_pcie_pipe_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_0_pipe_clk_src",
> - .parent_names = (const char *[]) { "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo",
> + },
> .num_parents = 1,
> .ops = &clk_rcg2_ops,
> },
> @@ -843,10 +792,11 @@ static struct clk_rcg2 pcie_1_aux_clk_src = {
> .mnd_width = 8,
> .hid_width = 5,
> .freq_tbl = ftbl_pcie_1_aux_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_1_aux_clk_src",
> - .parent_names = (const char *[]) { "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo",
> + },
> .num_parents = 1,
> .ops = &clk_rcg2_ops,
> },
> @@ -856,10 +806,11 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = {
> .cmd_rcgr = 0x1b5c,
> .hid_width = 5,
> .freq_tbl = ftbl_pcie_pipe_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "pcie_1_pipe_clk_src",
> - .parent_names = (const char *[]) { "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo",
> + },
> .num_parents = 1,
> .ops = &clk_rcg2_ops,
> },
> @@ -875,10 +826,9 @@ static struct clk_rcg2 pdm2_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_pdm2_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "pdm2_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -902,10 +852,9 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_gpll4_map,
> .freq_tbl = ftbl_sdcc1_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc1_apps_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll4,
> + .parent_data = gcc_xo_gpll0_gpll4,
> .num_parents = 3,
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -928,10 +877,9 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc2_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -943,10 +891,9 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc3_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -958,10 +905,9 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc4_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -977,10 +923,11 @@ static struct clk_rcg2 tsif_ref_clk_src = {
> .mnd_width = 8,
> .hid_width = 5,
> .freq_tbl = ftbl_tsif_ref_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "tsif_ref_clk_src",
> - .parent_names = (const char *[]) { "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo",
> + },
> .num_parents = 1,
> .ops = &clk_rcg2_ops,
> },
> @@ -997,10 +944,9 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "usb30_mock_utmi_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -1015,10 +961,11 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
> .cmd_rcgr = 0x1414,
> .hid_width = 5,
> .freq_tbl = ftbl_usb3_phy_aux_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "usb3_phy_aux_clk_src",
> - .parent_names = (const char *[]) { "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo",
> + },
> .num_parents = 1,
> .ops = &clk_rcg2_ops,
> },
> @@ -1034,10 +981,9 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
> .hid_width = 5,
> .parent_map = gcc_xo_gpll0_map,
> .freq_tbl = ftbl_usb_hs_system_clk_src,
> - .clkr.hw.init = &(struct clk_init_data)
> - {
> + .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hs_system_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = 2,
> .ops = &clk_rcg2_ops,
> },
> @@ -1049,8 +995,7 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
> .clkr = {
> .enable_reg = 0x1484,
> .enable_mask = BIT(17),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_ahb_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1062,12 +1007,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x0648,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup1_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup1_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1080,12 +1022,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x0644,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup1_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup1_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1098,12 +1037,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x06c8,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup2_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup2_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1116,12 +1052,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x06c4,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup2_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup2_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1134,12 +1067,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x0748,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup3_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup3_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1152,12 +1082,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x0744,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup3_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup3_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1170,12 +1097,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x07c8,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup4_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup4_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1188,12 +1112,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x07c4,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup4_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup4_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1206,12 +1127,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x0848,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup5_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup5_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1224,12 +1142,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x0844,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup5_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup5_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1242,12 +1157,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x08c8,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup6_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup6_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1260,12 +1172,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x08c4,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup6_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_qup6_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1278,12 +1187,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> .clkr = {
> .enable_reg = 0x0684,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart1_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_uart1_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1296,12 +1202,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> .clkr = {
> .enable_reg = 0x0704,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart2_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_uart2_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1314,12 +1217,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
> .clkr = {
> .enable_reg = 0x0784,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart3_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_uart3_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1332,12 +1232,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
> .clkr = {
> .enable_reg = 0x0804,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart4_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_uart4_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1350,12 +1247,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
> .clkr = {
> .enable_reg = 0x0884,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart5_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_uart5_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1368,12 +1262,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
> .clkr = {
> .enable_reg = 0x0904,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart6_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp1_uart6_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1387,8 +1278,7 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
> .clkr = {
> .enable_reg = 0x1484,
> .enable_mask = BIT(15),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_ahb_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1400,12 +1290,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x0988,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup1_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup1_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1418,12 +1305,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x0984,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup1_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup1_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1436,12 +1320,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x0a08,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup2_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup2_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1454,12 +1335,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x0a04,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup2_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup2_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1472,12 +1350,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x0a88,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup3_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup3_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1490,12 +1365,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x0a84,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup3_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup3_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1508,12 +1380,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x0b08,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup4_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup4_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1526,12 +1395,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x0b04,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup4_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup4_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1544,12 +1410,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x0b88,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup5_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup5_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1562,12 +1425,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x0b84,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup5_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup5_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1580,12 +1440,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
> .clkr = {
> .enable_reg = 0x0c08,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup6_i2c_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup6_i2c_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1598,12 +1455,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
> .clkr = {
> .enable_reg = 0x0c04,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_qup6_spi_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_qup6_spi_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1616,12 +1470,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
> .clkr = {
> .enable_reg = 0x09c4,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart1_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_uart1_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1634,12 +1485,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
> .clkr = {
> .enable_reg = 0x0a44,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart2_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_uart2_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1652,12 +1500,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
> .clkr = {
> .enable_reg = 0x0ac4,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart3_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_uart3_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1670,12 +1515,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
> .clkr = {
> .enable_reg = 0x0b44,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart4_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_uart4_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1688,12 +1530,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
> .clkr = {
> .enable_reg = 0x0bc4,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart5_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_uart5_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1706,12 +1545,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
> .clkr = {
> .enable_reg = 0x0c44,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp2_uart6_apps_clk",
> - .parent_names = (const char *[]) {
> - "blsp2_uart6_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1724,12 +1560,9 @@ static struct clk_branch gcc_gp1_clk = {
> .clkr = {
> .enable_reg = 0x1900,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_gp1_clk",
> - .parent_names = (const char *[]) {
> - "gp1_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1742,12 +1575,9 @@ static struct clk_branch gcc_gp2_clk = {
> .clkr = {
> .enable_reg = 0x1940,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_gp2_clk",
> - .parent_names = (const char *[]) {
> - "gp2_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1760,12 +1590,9 @@ static struct clk_branch gcc_gp3_clk = {
> .clkr = {
> .enable_reg = 0x1980,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_gp3_clk",
> - .parent_names = (const char *[]) {
> - "gp3_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1778,8 +1605,7 @@ static struct clk_branch gcc_lpass_q6_axi_clk = {
> .clkr = {
> .enable_reg = 0x0280,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_lpass_q6_axi_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1791,8 +1617,7 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
> .clkr = {
> .enable_reg = 0x0284,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_mss_q6_bimc_axi_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1804,12 +1629,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
> .clkr = {
> .enable_reg = 0x1ad4,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_aux_clk",
> - .parent_names = (const char *[]) {
> - "pcie_0_aux_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1822,8 +1644,7 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
> .clkr = {
> .enable_reg = 0x1ad0,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_cfg_ahb_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1835,8 +1656,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
> .clkr = {
> .enable_reg = 0x1acc,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_mstr_axi_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1849,12 +1669,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
> .clkr = {
> .enable_reg = 0x1ad8,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_pipe_clk",
> - .parent_names = (const char *[]) {
> - "pcie_0_pipe_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1868,8 +1685,7 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
> .clkr = {
> .enable_reg = 0x1ac8,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_slv_axi_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1881,12 +1697,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
> .clkr = {
> .enable_reg = 0x1b54,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_aux_clk",
> - .parent_names = (const char *[]) {
> - "pcie_1_aux_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1899,8 +1712,7 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
> .clkr = {
> .enable_reg = 0x1b54,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_cfg_ahb_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1912,8 +1724,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
> .clkr = {
> .enable_reg = 0x1b50,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_mstr_axi_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1926,12 +1737,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
> .clkr = {
> .enable_reg = 0x1b58,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_pipe_clk",
> - .parent_names = (const char *[]) {
> - "pcie_1_pipe_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1944,8 +1752,7 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
> .clkr = {
> .enable_reg = 0x1b48,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_slv_axi_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1957,12 +1764,9 @@ static struct clk_branch gcc_pdm2_clk = {
> .clkr = {
> .enable_reg = 0x0ccc,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pdm2_clk",
> - .parent_names = (const char *[]) {
> - "pdm2_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -1975,8 +1779,7 @@ static struct clk_branch gcc_pdm_ahb_clk = {
> .clkr = {
> .enable_reg = 0x0cc4,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_pdm_ahb_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -1988,12 +1791,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
> .clkr = {
> .enable_reg = 0x04c4,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc1_apps_clk",
> - .parent_names = (const char *[]) {
> - "sdcc1_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2006,8 +1806,7 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
> .clkr = {
> .enable_reg = 0x04c8,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc1_ahb_clk",
> .parent_names = (const char *[]){
> "periph_noc_clk_src",
> @@ -2023,8 +1822,7 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
> .clkr = {
> .enable_reg = 0x0508,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc2_ahb_clk",
> .parent_names = (const char *[]){
> "periph_noc_clk_src",
> @@ -2040,12 +1838,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
> .clkr = {
> .enable_reg = 0x0504,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc2_apps_clk",
> - .parent_names = (const char *[]) {
> - "sdcc2_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2058,8 +1853,7 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
> .clkr = {
> .enable_reg = 0x0548,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc3_ahb_clk",
> .parent_names = (const char *[]){
> "periph_noc_clk_src",
> @@ -2075,12 +1869,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
> .clkr = {
> .enable_reg = 0x0544,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc3_apps_clk",
> - .parent_names = (const char *[]) {
> - "sdcc3_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2093,8 +1884,7 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
> .clkr = {
> .enable_reg = 0x0588,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc4_ahb_clk",
> .parent_names = (const char *[]){
> "periph_noc_clk_src",
> @@ -2110,12 +1900,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
> .clkr = {
> .enable_reg = 0x0584,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc4_apps_clk",
> - .parent_names = (const char *[]) {
> - "sdcc4_apps_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2128,12 +1915,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
> .clkr = {
> .enable_reg = 0x1d7c,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sys_noc_ufs_axi_clk",
> - .parent_names = (const char *[]) {
> - "ufs_axi_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2146,12 +1930,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
> .clkr = {
> .enable_reg = 0x03fc,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_sys_noc_usb3_axi_clk",
> - .parent_names = (const char *[]) {
> - "usb30_master_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2164,8 +1945,7 @@ static struct clk_branch gcc_tsif_ahb_clk = {
> .clkr = {
> .enable_reg = 0x0d84,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_tsif_ahb_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -2177,12 +1957,9 @@ static struct clk_branch gcc_tsif_ref_clk = {
> .clkr = {
> .enable_reg = 0x0d88,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_tsif_ref_clk",
> - .parent_names = (const char *[]) {
> - "tsif_ref_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2195,8 +1972,7 @@ static struct clk_branch gcc_ufs_ahb_clk = {
> .clkr = {
> .enable_reg = 0x1d4c,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_ahb_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -2208,12 +1984,9 @@ static struct clk_branch gcc_ufs_axi_clk = {
> .clkr = {
> .enable_reg = 0x1d48,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_axi_clk",
> - .parent_names = (const char *[]) {
> - "ufs_axi_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2226,12 +1999,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
> .clkr = {
> .enable_reg = 0x1d54,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_rx_cfg_clk",
> - .parent_names = (const char *[]) {
> - "ufs_axi_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2245,8 +2015,7 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
> .clkr = {
> .enable_reg = 0x1d60,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_rx_symbol_0_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -2259,8 +2028,7 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
> .clkr = {
> .enable_reg = 0x1d64,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_rx_symbol_1_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -2272,12 +2040,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
> .clkr = {
> .enable_reg = 0x1d50,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_tx_cfg_clk",
> - .parent_names = (const char *[]) {
> - "ufs_axi_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2291,8 +2056,7 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
> .clkr = {
> .enable_reg = 0x1d58,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_tx_symbol_0_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -2305,8 +2069,7 @@ static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
> .clkr = {
> .enable_reg = 0x1d5c,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_ufs_tx_symbol_1_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -2318,9 +2081,13 @@ static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
> .clkr = {
> .enable_reg = 0x04ac,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_usb2_hs_phy_sleep_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep",
> + .name = "sleep"
> + },
> + .num_parents = 1,
> .ops = &clk_branch2_ops,
> },
> },
> @@ -2331,12 +2098,9 @@ static struct clk_branch gcc_usb30_master_clk = {
> .clkr = {
> .enable_reg = 0x03c8,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_usb30_master_clk",
> - .parent_names = (const char *[]) {
> - "usb30_master_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2349,12 +2113,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
> .clkr = {
> .enable_reg = 0x03d0,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_usb30_mock_utmi_clk",
> - .parent_names = (const char *[]) {
> - "usb30_mock_utmi_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2367,9 +2128,13 @@ static struct clk_branch gcc_usb30_sleep_clk = {
> .clkr = {
> .enable_reg = 0x03cc,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_usb30_sleep_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep",
> + .name = "sleep"
> + },
> + .num_parents = 1,
> .ops = &clk_branch2_ops,
> },
> },
> @@ -2380,12 +2145,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
> .clkr = {
> .enable_reg = 0x1408,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_usb3_phy_aux_clk",
> - .parent_names = (const char *[]) {
> - "usb3_phy_aux_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2398,8 +2160,7 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
> .clkr = {
> .enable_reg = 0x0488,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hs_ahb_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -2411,12 +2172,9 @@ static struct clk_branch gcc_usb_hs_system_clk = {
> .clkr = {
> .enable_reg = 0x0484,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hs_system_clk",
> - .parent_names = (const char *[]) {
> - "usb_hs_system_clk_src",
> - },
> + .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_branch2_ops,
> @@ -2429,8 +2187,7 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
> .clkr = {
> .enable_reg = 0x1a84,
> .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data)
> - {
> + .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_phy_cfg_ahb2phy_clk",
> .ops = &clk_branch2_ops,
> },
> @@ -2663,13 +2420,6 @@ MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
>
> static int gcc_msm8994_probe(struct platform_device *pdev)
> {
> - struct device *dev = &pdev->dev;
> - struct clk *clk;
> -
> - clk = devm_clk_register(dev, &xo.hw);
> - if (IS_ERR(clk))
> - return PTR_ERR(clk);
> -
> return qcom_cc_probe(pdev, &gcc_msm8994_desc);
> }
>
> --
> 2.33.0
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
` (7 preceding siblings ...)
2021-08-29 19:36 ` [PATCH RESEND v2 9/9] clk: qcom: gcc-msm8994: Add a quirk for a different SDCC configuration Konrad Dybcio
@ 2021-08-30 11:49 ` Rob Herring
8 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2021-08-30 11:49 UTC (permalink / raw)
To: Konrad Dybcio
Cc: devicetree, Stephen Boyd, jamipkettunen, Bjorn Andersson,
Taniya Das, linux-kernel, angelogioacchino.delregno,
Michael Turquette, Rob Herring, linux-clk, linux-arm-msm,
~postmarketos/upstreaming, Andy Gross, martin.botka,
marijn.suijten
On Sun, 29 Aug 2021 21:36:08 +0200, Konrad Dybcio wrote:
> Add documentation for the MSM8994 GCC driver.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> No changes since the original v2, only added Rob's A-b
>
> .../bindings/clock/qcom,gcc-msm8994.yaml | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.example.dt.yaml: clock-controller@300000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1522007
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-08-30 11:49 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-29 19:36 [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 2/9] clk: qcom: gcc-msm8994: Modernize the driver Konrad Dybcio
2021-08-29 19:52 ` Stephen Boyd
2021-08-29 19:55 ` Konrad Dybcio
2021-08-29 20:47 ` Dmitry Baryshkov
2021-08-29 19:36 ` [PATCH RESEND v2 3/9] clk: qcom: gcc-msm8994: Fix up SPI QUP clocks Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 4/9] clk: qcom: gcc-msm8994: Add missing NoC clocks Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 5/9] clk: qcom: gcc-msm8994: Add missing clocks Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 6/9] clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 7/9] clk: qcom: gcc-msm8994: Add modem reset Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 8/9] clk: qcom: gcc-msm8994: Add proper msm8992 support Konrad Dybcio
2021-08-29 19:36 ` [PATCH RESEND v2 9/9] clk: qcom: gcc-msm8994: Add a quirk for a different SDCC configuration Konrad Dybcio
2021-08-29 19:50 ` Stephen Boyd
2021-08-30 11:49 ` [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver Rob Herring
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