From: Marijn Suijten <marijn.suijten@somainline.org>
To: phone-devel@vger.kernel.org
Cc: ~postmarketos/upstreaming@lists.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Martin Botka <martin.botka@somainline.org>,
Jami Kettunen <jami.kettunen@somainline.org>,
Pavel Dubrova <pashadubrova@gmail.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Andy Gross <agross@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 3/3] clk: qcom: gcc-sdm660: Remove transient global "xo" clock
Date: Sun, 29 Aug 2021 22:30:27 +0200 [thread overview]
Message-ID: <20210829203027.276143-4-marijn.suijten@somainline.org> (raw)
In-Reply-To: <20210829203027.276143-1-marijn.suijten@somainline.org>
The DSI PHY/PLL was relying on a global "xo" clock to be found, but the
real clock is named "xo_board" in the DT. The standard nowadays is to
never use global clock names anymore but require the firmware (DT) to
provide every clock binding explicitly with .fw_name. The DSI PLLs have
since been converted to this mechanism (specifically 14nm for SDM660)
and this transient clock can now be removed.
This issue was originally discovered in:
https://lore.kernel.org/linux-arm-msm/386db1a6-a1cd-3c7d-a88e-dc83f8a1be96@somainline.org/
and prevented the removal of "xo" at that time.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
drivers/clk/qcom/gcc-sdm660.c | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index 9b97425008ce..16fd16351f95 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -37,19 +37,6 @@ enum {
P_GPLL1_EARLY_DIV,
};
-static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "xo",
- .parent_data = &(const struct clk_parent_data) {
- .fw_name = "xo"
- },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-};
-
static struct clk_alpha_pll gpll0_early = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@@ -2281,7 +2268,6 @@ static struct gdsc pcie_0_gdsc = {
};
static struct clk_hw *gcc_sdm660_hws[] = {
- &xo.hw,
&gpll0_early_div.hw,
&gpll1_early_div.hw,
};
--
2.33.0
prev parent reply other threads:[~2021-08-29 20:30 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210829203027.276143-1-marijn.suijten@somainline.org>
2021-08-29 20:30 ` [PATCH 1/3] arm: dts: qcom: apq8064: Use 27MHz PXO clock as DSI PLL reference Marijn Suijten
2021-08-30 1:18 ` Dmitry Baryshkov
2021-08-30 8:28 ` Marijn Suijten
2021-08-30 13:24 ` Dmitry Baryshkov
2021-08-30 14:13 ` Marijn Suijten
2021-08-30 14:18 ` Dmitry Baryshkov
2021-08-30 14:25 ` Marijn Suijten
2021-08-30 15:17 ` Bjorn Andersson
2021-08-30 15:37 ` Marijn Suijten
2021-08-30 15:58 ` Bjorn Andersson
2021-08-30 18:33 ` Marijn Suijten
2021-08-29 20:30 ` [PATCH 2/3] drm/msm/dsi: Use "ref" fw clock instead of global name for VCO parent Marijn Suijten
2021-08-29 20:39 ` Dmitry Baryshkov
2021-08-29 21:53 ` Marijn Suijten
2021-08-30 1:17 ` Dmitry Baryshkov
2021-08-30 14:22 ` Marijn Suijten
2021-08-29 20:30 ` Marijn Suijten [this message]
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