linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Prathamesh Shete <pshete@nvidia.com>
To: <linus.walleij@linaro.org>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <ldewangan@nvidia.com>,
	<linux-gpio@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Cc: <smangipudi@nvidia.com>, <pshete@nvidia.com>
Subject: [PATCH 1/2] pinctrl: pimux: Add support to save and restore HW register
Date: Tue, 31 Aug 2021 10:58:33 +0530	[thread overview]
Message-ID: <20210831052834.4136-2-pshete@nvidia.com> (raw)
In-Reply-To: <20210831052834.4136-1-pshete@nvidia.com>

From: Laxman Dewangan <ldewangan@nvidia.com>

Add support to save and restore the pincontrol HW register
for GPIO mode configurations. This helps in changing the
pin configure only during suspend and restore in resume.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: pshete <pshete@nvidia.com>
---
 drivers/pinctrl/pinmux.c       | 24 ++++++++++++++++++++++++
 drivers/pinctrl/pinmux.h       | 18 ++++++++++++++++++
 include/linux/pinctrl/pinmux.h |  9 +++++++++
 3 files changed, 51 insertions(+)

diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 6cdbd9ccf2f0..66fc0ca22623 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -317,6 +317,30 @@ int pinmux_gpio_direction(struct pinctrl_dev *pctldev,
 	return ret;
 }
 
+int pinmux_gpio_save_config(struct pinctrl_dev *pctldev,
+			    struct pinctrl_gpio_range *range,
+			    unsigned pin)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+
+	if (ops->gpio_save_config)
+		return ops->gpio_save_config(pctldev, range, pin);
+
+	return 0;
+}
+
+int pinmux_gpio_restore_config(struct pinctrl_dev *pctldev,
+			       struct pinctrl_gpio_range *range,
+			       unsigned pin)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+
+	if (ops->gpio_restore_config)
+		return ops->gpio_restore_config(pctldev, range, pin);
+
+	return 0;
+}
+
 static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
 					const char *function)
 {
diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
index 78c3a31be882..425c31a0115b 100644
--- a/drivers/pinctrl/pinmux.h
+++ b/drivers/pinctrl/pinmux.h
@@ -31,6 +31,12 @@ int pinmux_map_to_setting(const struct pinctrl_map *map,
 void pinmux_free_setting(const struct pinctrl_setting *setting);
 int pinmux_enable_setting(const struct pinctrl_setting *setting);
 void pinmux_disable_setting(const struct pinctrl_setting *setting);
+int pinmux_gpio_save_config(struct pinctrl_dev *pctldev,
+			    struct pinctrl_gpio_range *range,
+			    unsigned pin);
+int pinmux_gpio_restore_config(struct pinctrl_dev *pctldev,
+			       struct pinctrl_gpio_range *range,
+			       unsigned pin);
 
 #else
 
@@ -89,6 +95,18 @@ static inline void pinmux_disable_setting(const struct pinctrl_setting *setting)
 {
 }
 
+int pinmux_gpio_save_config(struct pinctrl_dev *pctldev,
+			    struct pinctrl_gpio_range *range,
+			    unsigned pin)
+{
+	return 0;
+}
+int pinmux_gpio_restore_config(struct pinctrl_dev *pctldev,
+			       struct pinctrl_gpio_range *range,
+			       unsigned pin)
+{
+	return 0;
+}
 #endif
 
 #if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h
index 9a647fa5c8f1..cca87586d8c1 100644
--- a/include/linux/pinctrl/pinmux.h
+++ b/include/linux/pinctrl/pinmux.h
@@ -53,6 +53,8 @@ struct pinctrl_dev;
  *	depending on whether the GPIO is configured as input or output,
  *	a direction selector function may be implemented as a backing
  *	to the GPIO controllers that need pin muxing.
+ * @gpio_save_config: Save the GPIo configurations.
+ * @gpio_restore_config: Restore GPIO configurations.
  * @strict: do not allow simultaneous use of the same pin for GPIO and another
  *	function. Check both gpio_owner and mux_owner strictly before approving
  *	the pin request.
@@ -79,6 +81,13 @@ struct pinmux_ops {
 				   struct pinctrl_gpio_range *range,
 				   unsigned offset,
 				   bool input);
+	int (*gpio_save_config) (struct pinctrl_dev *pctldev,
+				 struct pinctrl_gpio_range *range,
+				 unsigned offset);
+	int (*gpio_restore_config) (struct pinctrl_dev *pctldev,
+				    struct pinctrl_gpio_range *range,
+				    unsigned offset);
+
 	bool strict;
 };
 
-- 
2.17.1


  reply	other threads:[~2021-08-31  5:29 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-31  5:28 [PATCH 0/2] pinctrl: support to save and restore GPIO conf Prathamesh Shete
2021-08-31  5:28 ` Prathamesh Shete [this message]
2021-08-31  8:13   ` [PATCH 1/2] pinctrl: pimux: Add support to save and restore HW register Mikko Perttunen
2021-08-31 14:28   ` kernel test robot
2021-08-31  5:28 ` [PATCH 2/2] pinctrl: tegra: Implement pinmux register save and restore Prathamesh Shete

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210831052834.4136-2-pshete@nvidia.com \
    --to=pshete@nvidia.com \
    --cc=jonathanh@nvidia.com \
    --cc=ldewangan@nvidia.com \
    --cc=linus.walleij@linaro.org \
    --cc=linux-gpio@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=smangipudi@nvidia.com \
    --cc=thierry.reding@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).