From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <lokeshvutla@ti.com>
Subject: [PATCH 04/14] phy: cadence: Sierra: Add support to get SSC type from device tree
Date: Fri, 3 Sep 2021 07:00:44 +0200 [thread overview]
Message-ID: <20210903050054.25627-5-sjakhade@cadence.com> (raw)
In-Reply-To: <20210903050054.25627-1-sjakhade@cadence.com>
Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 7e0f36dabc95..31e5d428dc03 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -238,6 +238,7 @@ struct cdns_sierra_inst {
u32 num_lanes;
u32 mlane;
struct reset_control *lnk_rst;
+ enum cdns_sierra_ssc_mode ssc_mode;
};
struct cdns_reg_pairs {
@@ -360,7 +361,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
const struct cdns_sierra_data *init_data = phy->init_data;
struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
enum cdns_sierra_phy_type phy_type = ins->phy_type;
- enum cdns_sierra_ssc_mode ssc = EXTERNAL_SSC;
+ enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
const struct cdns_reg_pairs *reg_pairs;
struct regmap *regmap;
u32 num_regs;
@@ -623,6 +624,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
return -EINVAL;
}
+ inst->ssc_mode = EXTERNAL_SSC;
+ of_property_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode);
+
return 0;
}
--
2.26.1
next prev parent reply other threads:[~2021-09-03 5:01 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-03 5:00 [PATCH 00/14] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 01/14] phy: cadence: Sierra: Use of_device_get_match_data() to get driver data Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 02/14] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 03/14] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Swapnil Jakhade
2021-09-03 16:12 ` Rob Herring
2021-09-03 5:00 ` Swapnil Jakhade [this message]
2021-09-03 5:00 ` [PATCH 05/14] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 06/14] phy: cadence: Sierra: Add PHY PCS common register configurations Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 07/14] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 08/14] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 09/14] phy: cadence: Sierra: Update single link PCIe register configuration Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 10/14] phy: cadence: Sierra: Fix to get correct parent for mux clocks Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 11/14] phy: cadence: Sierra: Add support for PHY multilink configurations Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 12/14] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 13/14] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock Swapnil Jakhade
2021-09-03 5:00 ` [PATCH 14/14] phy: cadence: Sierra: Add support for derived reference clock output Swapnil Jakhade
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