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Sat, 4 Sep 2021 06:50:22 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 41BC34C050; Sat, 4 Sep 2021 06:50:15 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.43.55.112]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sat, 4 Sep 2021 06:50:14 +0000 (GMT) From: Kajol Jain To: mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, jolsa@kernel.org, namhyung@kernel.org, linux-perf-users@vger.kernel.org, ak@linux.intel.com Cc: maddy@linux.ibm.com, atrajeev@linux.vnet.ibm.com, kjain@linux.ibm.com, rnsastry@linux.ibm.com, yao.jin@linux.intel.com, ast@kernel.org, daniel@iogearbox.net, songliubraving@fb.com, kan.liang@linux.intel.com, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, paulus@samba.org Subject: [PATCH 2/3] perf: Add macros to specify onchip L2/L3 accesses Date: Sat, 4 Sep 2021 12:19:31 +0530 Message-Id: <20210904064932.307610-2-kjain@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210904064932.307610-1-kjain@linux.ibm.com> References: <20210904064932.307610-1-kjain@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: vfn5RswQX45GrUynouvKzwWboh437Mul X-Proofpoint-ORIG-GUID: 8rwH5_WniquqzoTDEcortWe3VSP-j7cI X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790 definitions=2021-09-04_02:2021-09-03,2021-09-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 spamscore=0 malwarescore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 clxscore=1015 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2108310000 definitions=main-2109040044 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add couple of new macros to represent onchip L2 and onchip L3 accesses. Patch also adds the decoding strings in the mem_lvlnum data structure. Signed-off-by: Kajol Jain --- tools/include/uapi/linux/perf_event.h | 4 +++- tools/perf/util/mem-events.c | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h index f92880a15645..030b3e990ac3 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -1265,7 +1265,9 @@ union perf_mem_data_src { #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ -/* 5-0xa available */ +#define PERF_MEM_LVLNUM_OC_L2 0x05 /* On Chip L2 */ +#define PERF_MEM_LVLNUM_OC_L3 0x06 /* On Chip L3 */ +/* 7-0xa available */ #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index f0e75df72b80..f846a91220c2 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -294,6 +294,8 @@ static const char * const mem_lvl[] = { }; static const char * const mem_lvlnum[] = { + [PERF_MEM_LVLNUM_OC_L2] = "OnChip L2", + [PERF_MEM_LVLNUM_OC_L3] = "OnChip L3", [PERF_MEM_LVLNUM_ANY_CACHE] = "Any cache", [PERF_MEM_LVLNUM_LFB] = "LFB", [PERF_MEM_LVLNUM_RAM] = "RAM", -- 2.26.2