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Ivanov" , "Lee, Chun-Yi" , Chester Lin Subject: [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Date: Wed, 8 Sep 2021 14:45:20 +0800 Message-ID: <20210908064528.922-1-clin@suse.com> X-Mailer: git-send-email 2.30.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM0PR03CA0032.eurprd03.prod.outlook.com (2603:10a6:208:14::45) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost (36.224.129.215) by AM0PR03CA0032.eurprd03.prod.outlook.com (2603:10a6:208:14::45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend Transport; Wed, 8 Sep 2021 06:45:54 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 07bef97b-b25b-4b4e-6c1c-08d972944ee5 X-MS-TrafficTypeDiagnostic: VI1PR04MB4000: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?kMwZZkRQ4KIrlK+lxpjSOJo2BzP48Gyl5U8/yJKZutMOXkuBiHW63b6rK2BX?= =?us-ascii?Q?kzfussxwZ9uAu1h2mZ8p/0NSDiMrJL8nPP8WtQe0+grHqpS2SUWgt8zuxZ06?= =?us-ascii?Q?vAlc6lR/2jYsUXvbOG+HbT6Uyg1ZBnZJFuYW3hJRKHO9DIxPHSpRafb15jGu?= =?us-ascii?Q?ZpPD9s3g6tk5DmOAdvTZi3yyqz5lnD+MuKXAgMq7j++GHJQyh0+02JDvyRjf?= =?us-ascii?Q?QqmPeJxDpS0ZfAMDCmeWsKWoXOTL+6hK9WBcLPOU/AY6ySm4r5IszzsjW6Eo?= =?us-ascii?Q?7fSj6Pr6SCCGLJpwNBtln6gUs0jdjvUA5mnk5cIb4eu9+l3Sc/uJN6M+Z6Un?= =?us-ascii?Q?zsl6mjNuA0sV50hnfI3mfjiMPCtZTohPQVUtLEp4VCyfs2yBseD7oWMj7nHa?= =?us-ascii?Q?79D6y3u6c9e92rN5PbEPuVhrNJJj851b5BImJj4yyyFgVp6H4/YsAngJVxZA?= =?us-ascii?Q?Z7q3FFt7/7B3QmJzbGINo2Ijf2M7WwXU8PhvWcImjqXKl4n3lGz6JIWmbzHU?= =?us-ascii?Q?mVzCg+eD8TdfOYL9shtaYc2vezbsHPg0qIESVsffl8n7DkRGYZVKcVqcEZvE?= =?us-ascii?Q?5SJdn7Ww3TABR5FKSoekUZ2XlHsYkWLNFLEUj/cGi8H6kH8I2f48oV98Y31y?= =?us-ascii?Q?ID9ZJBn99HZ3vD3eK5p6bbAmXALBpBoxSNUevu+JPYhAgjvKusW/WtgtQIQ0?= =?us-ascii?Q?YOwjTEH7fB3pZpeQGNSuSOQbJ8SGb09thQRO8cmUUBMOu6HJlRp2X7k3+5g9?= =?us-ascii?Q?/HlTL9px37B0k27mbhpkC5cLO3q0tpSU45WO9wD6dA8meYYImsyvAXPalMid?= =?us-ascii?Q?vbrp4uYM1LjqX5KY9MbGZpy1iL/INjrSinO5tuhxGMjSsPWTgosDFkHUt5sS?= =?us-ascii?Q?1m4j0s+RAfrrEPAlbZPrM+gUVCYU3/uwgQ2ubXn6va95NIDT+ZmhedjKZBMc?= =?us-ascii?Q?b7JhXmaUWWiMM2oH5DlZ5N6PVU2rU4RxumIEKcxNtpQVMsD/mqYbKTgPTYEJ?= =?us-ascii?Q?y0nEb/BOHIgsc6r4CZcfgrwQk9uH2aDH07vrUFzCpwyzObaDiwijv6DFnkgS?= =?us-ascii?Q?WpseD8vrbGu+cjctLNkRBXjMC99HmWRJwhinYmCpVgau+KM4u3MvEYxcT8Z9?= =?us-ascii?Q?gzYmi9Irv1YSYTUAlUY9CKjpqQvrT6yhld5l4DbuarkX7jAAA8ORedzq1SyL?= =?us-ascii?Q?RYT/HvdTphPYHX0DvYDW+JUDNv8nPpZJ4bilXWjXZSptP4WIcin+1yuLWb9G?= =?us-ascii?Q?IhMBOQ7lywb+6kq70v9t1uB+PnrgY1EUfqCX4DsuChE53yAaNr30KhrEHVJ7?= =?us-ascii?Q?A1aKIDXn5xWIZEBtpYwyXm4R?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 07bef97b-b25b-4b4e-6c1c-08d972944ee5 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 06:45:56.0116 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4hlizc3gyy4Kj9cFGdjOhQd0IiEGPKqrRFAI0/ZasEpl4sKWK+qqVKVkdlmYNukd X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4000 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, Here I'd like to propose a patchset, which is initial upstream support for = NXP S32G2. S32G is a processor family developed by NXP for automotive solutions= , such as vehicle networking and automotive high-performance processing. This series focuses on S32G2, which is the latest generation we can find at the moment. As the first round to support S32G2, this patchset only enables bas= ic components and interfaces the SoC must have while kernel booting, which aim= s to have minimum hardware enablement for these two boards, S32G-VNP-EVB and S32G-VNP-RDB2. The concepts of how these boards work are originated from th= e downstream kernel tree[1] developed by NXP, which provides lots of details about the SoC S32G274A and its integrated boards. This series has been verified with downstream ATF[2] & U-Boot[3] based on the ATF boot flow. Thanks, Chester [1] https://source.codeaurora.org/external/autobsps32/linux/ [2] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/ [3] https://source.codeaurora.org/external/autobsps32/u-boot/ Changes in v2: - dt-bindings: - Rename the compatible vendor string to "nxp," for s32g2. - Drop the specific description "S32V234 SoC". - Fill my name in the maintainer field. I tried to contact the authors of fsl,s32-linflexuart.txt but got no response. - Remove redundant minItems/maxItems from compatible properties. - Remove the redundant example from fsl,s32-linflexuart.yaml. - dtsi/dts: - Add a SoC description in s32g2.dtsi. - Add an interrupt-affinity to the pmu node. - Move the psci node into the "/firmware" node. - Remove the redundant properties and white lines in DT. - Remove the wrong interrupt specifier from the gic node. - Specify the range and cell-size of /soc [0 - 4 GiB]. - Correct the reserved size of GICR to 512Kbytes [0x80000]. - Add new Signed-off-by to the DT uart patch. - Fix copyright strings. - Revise reg properties based on new cell-size. - Move the serial/uart aliases from the SoC .dtsi to board .dts files. - Correct the model string of RDB2. - Add comments for the uart markings on PCB. - Adjust RAM size comments of memory nodes. - Convert reg addresses of memory nodes into hex format. - MAINTAINERS - Add information of reviewers. Chester Lin (8): dt-bindings: arm: fsl: add NXP S32G2 boards dt-bindings: serial: fsl-linflexuart: convert to json-schema format dt-bindings: serial: fsl-linflexuart: add compatible for S32G2 arm64: dts: add NXP S32G2 support arm64: dts: s32g2: add serial/uart support arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support arm64: dts: s32g2: add memory nodes for evb and rdb2 MAINTAINERS: add an entry for NXP S32G boards .../devicetree/bindings/arm/fsl.yaml | 7 + .../bindings/serial/fsl,s32-linflexuart.txt | 22 ---- .../bindings/serial/fsl,s32-linflexuart.yaml | 48 +++++++ MAINTAINERS | 9 ++ arch/arm64/boot/dts/freescale/Makefile | 2 + arch/arm64/boot/dts/freescale/s32g2.dtsi | 124 ++++++++++++++++++ .../arm64/boot/dts/freescale/s32g274a-evb.dts | 34 +++++ .../boot/dts/freescale/s32g274a-rdb2.dts | 40 ++++++ 8 files changed, 264 insertions(+), 22 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linfle= xuart.txt create mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linfle= xuart.yaml create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-evb.dts create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts --=20 2.30.0