[PATCH v2 00/10] Improve support for AMD SPI controllers

[Lucas Tanure <tanureal@opensource.cirrus.com>]

Add support for AMDI0062 and correctly fill the FIFO buffer with
the whole message.

With a message of AMD_SPI_FIFO_SIZE bytes or less, copying all
transfers to the FIFO guarantees that the message is sent over
one CS. Because the controller has an automatic CS that is only
activated during the transmission of the FIFO.

And the controller is half-duplex in that it cannot read data
while it is sending data. But the FIFO is full-duplex, the writes
and reads must be queued and executed together, where it can only
have one write and one read per FIFO, and the writing part is
executed first. Therefore transfers can be put together in the
FIFO unless there is a write after read, which will need to be
executed in another CS.

v2 changes:
Replace flag SPI_CONTROLLER_CS_PER_TRANSFER by checking
spi_max_message_size
Add flag for controllers that can't TX after RX in the same
message
SPI controller now expects a message that always can fit in
FIFO
Add a new patch for configuring the SPI speed


Lucas Tanure (9):
  regmap: spi: Set regmap max raw r/w from max_transfer_size
  regmap: spi: Check raw_[read|write] against max message size
  spi: Add flag for no TX after a RX in the same Chip Select
  spi: amd: Refactor code to use less spi_master_get_devdata
  spi: amd: Refactor amd_spi_busy_wait
  spi: amd: Remove unneeded variable
  spi: amd: Check for idle bus before execute opcode
  spi: amd: Fill FIFO buffer with the whole message
  spi: amd: Configure the SPI speed

Nehal Bakulchandra Shah (1):
  spi: amd: Add support for latest platform

 drivers/base/regmap/regmap-spi.c |  40 ++-
 drivers/base/regmap/regmap.c     |  15 +
 drivers/spi/spi-amd.c            | 498 ++++++++++++++++++++++---------
 drivers/spi/spi.c                |  11 +
 include/linux/regmap.h           |   3 +
 include/linux/spi/spi.h          |   1 +
 6 files changed, 421 insertions(+), 147 deletions(-)

--
2.33.0