From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDE8BC433F5 for ; Fri, 10 Sep 2021 01:54:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B2C87610A3 for ; Fri, 10 Sep 2021 01:54:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229514AbhIJBzL (ORCPT ); Thu, 9 Sep 2021 21:55:11 -0400 Received: from mga07.intel.com ([134.134.136.100]:39045 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229461AbhIJBzK (ORCPT ); Thu, 9 Sep 2021 21:55:10 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10102"; a="284668191" X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="284668191" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 18:54:00 -0700 X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="548935759" Received: from jianjunz-mobl2.ccr.corp.intel.com (HELO localhost) ([10.249.170.205]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2021 18:53:54 -0700 Date: Fri, 10 Sep 2021 09:53:51 +0800 From: Yu Zhang To: Sean Christopherson Cc: Hou Wenlong , kvm@vger.kernel.org, Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H. Peter Anvin" , Jan Kiszka , Avi Kivity , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" Subject: Re: [PATCH v2 1/3] kvm: x86: Introduce hypercall x86 ops for handling hypercall not in cpl0 Message-ID: <20210910015351.yxvgv2nedgojmmeo@linux.intel.com> References: <04a337801ad5aaa54144dc57df8ee2fc32bc9c4e.1631188011.git.houwenlong93@linux.alibaba.com> <20210909163901.2vvozmkuxjcgabs5@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 09, 2021 at 05:09:11PM +0000, Sean Christopherson wrote: > On Fri, Sep 10, 2021, Yu Zhang wrote: > > On Thu, Sep 09, 2021 at 07:55:23PM +0800, Hou Wenlong wrote: > > > Per Intel's SDM, use vmcall instruction in non VMX operation for cpl3 > > > it should trigger a #UD. And in VMX root operation, it should > > > > Are you sure? IIRC, vmcall will always cause VM exit as long as CPU > > is in non-root mode(regardless the CPL). > > Correct, VMCALL unconditionally causes VM-Exit in non-root mode, but Hou is > referring to the first fault condition of "non VMX operation". The intent of the > patch is to emulate hardware behavior for CPL>0: if L1 is not in VMX operation, > a.k.a. not post-VMXON, then #UD, else #GP (because VMCALL #GPs at CPL>0 in VMX > root). Oh, I see. It's to make the virtualized world more real. But like you said, it's not KVM's target. And doing that could cause more problems - a PV guest expects the VMCALL to succeed, regardless it has VMX capability or its VMX is on or not. Thanks for the explaination. B.R. Yu