From: Billy Tsai <billy_tsai@aspeedtech.com>
To: <jic23@kernel.org>, <lars@metafoo.de>, <pmeerw@pmeerw.net>,
<robh+dt@kernel.org>, <joel@jms.id.au>, <andrew@aj.id.au>,
<p.zabel@pengutronix.de>, <lgirdwood@gmail.com>,
<broonie@kernel.org>, <linux-iio@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>
Cc: <BMC-SW@aspeedtech.com>
Subject: [v6 08/11] iio: adc: aspeed: Add func to set sampling rate.
Date: Mon, 13 Sep 2021 15:53:34 +0800 [thread overview]
Message-ID: <20210913075337.19991-9-billy_tsai@aspeedtech.com> (raw)
In-Reply-To: <20210913075337.19991-1-billy_tsai@aspeedtech.com>
Add the function to set the sampling rate and keep the sampling period
for a driver used to wait the fresh value.
In addition, since the ADC clock is required when initializing the ADC
device, move clk_prepare_enable ahead of the initialization phase.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
drivers/iio/adc/aspeed_adc.c | 58 ++++++++++++++++++++++++------------
1 file changed, 39 insertions(+), 19 deletions(-)
diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
index 262b5f80c728..cf1e0be9d11f 100644
--- a/drivers/iio/adc/aspeed_adc.c
+++ b/drivers/iio/adc/aspeed_adc.c
@@ -73,6 +73,12 @@
#define ASPEED_ADC_INIT_POLLING_TIME 500
#define ASPEED_ADC_INIT_TIMEOUT 500000
+/*
+ * When the sampling rate is too high, the ADC may not have enough charging
+ * time, resulting in a low voltage value. Thus, the default uses a slow
+ * sampling rate for most use cases.
+ */
+#define ASPEED_ADC_DEF_SAMPLING_RATE 65000
struct aspeed_adc_model_data {
const char *model_name;
@@ -96,6 +102,7 @@ struct aspeed_adc_data {
struct clk_hw *clk_scaler;
struct reset_control *rst;
int vref_mv;
+ u32 sample_period_ns;
};
#define ASPEED_CHAN(_idx, _data_reg_addr) { \
@@ -127,6 +134,24 @@ static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
ASPEED_CHAN(15, 0x2E),
};
+static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate)
+{
+ struct aspeed_adc_data *data = iio_priv(indio_dev);
+
+ if (rate < data->model_data->min_sampling_rate ||
+ rate > data->model_data->max_sampling_rate)
+ return -EINVAL;
+ /* Each sampling needs 12 clocks to convert.*/
+ clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE);
+ rate = clk_get_rate(data->clk_scaler->clk);
+ data->sample_period_ns = DIV_ROUND_UP_ULL(
+ (u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate);
+ dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate,
+ data->sample_period_ns);
+
+ return 0;
+}
+
static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
@@ -157,17 +182,9 @@ static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
- struct aspeed_adc_data *data = iio_priv(indio_dev);
-
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
- if (val < data->model_data->min_sampling_rate ||
- val > data->model_data->max_sampling_rate)
- return -EINVAL;
-
- clk_set_rate(data->clk_scaler->clk,
- val * ASPEED_CLOCKS_PER_SAMPLE);
- return 0;
+ return aspeed_adc_set_sampling_rate(indio_dev, val);
case IIO_CHAN_INFO_SCALE:
case IIO_CHAN_INFO_RAW:
@@ -392,6 +409,19 @@ static int aspeed_adc_probe(struct platform_device *pdev)
if (ret)
return ret;
+ ret = clk_prepare_enable(data->clk_scaler->clk);
+ if (ret)
+ return ret;
+ ret = devm_add_action_or_reset(data->dev,
+ aspeed_adc_clk_disable_unprepare,
+ data->clk_scaler->clk);
+ if (ret)
+ return ret;
+ ret = aspeed_adc_set_sampling_rate(indio_dev,
+ ASPEED_ADC_DEF_SAMPLING_RATE);
+ if (ret)
+ return ret;
+
adc_engine_control_reg_val =
readl(data->base + ASPEED_REG_ENGINE_CONTROL);
adc_engine_control_reg_val |=
@@ -418,16 +448,6 @@ static int aspeed_adc_probe(struct platform_device *pdev)
return ret;
}
- ret = clk_prepare_enable(data->clk_scaler->clk);
- if (ret)
- return ret;
-
- ret = devm_add_action_or_reset(data->dev,
- aspeed_adc_clk_disable_unprepare,
- data->clk_scaler->clk);
- if (ret)
- return ret;
-
/* Start all channels in normal mode. */
adc_engine_control_reg_val =
readl(data->base + ASPEED_REG_ENGINE_CONTROL);
--
2.25.1
next prev parent reply other threads:[~2021-09-13 7:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 7:53 [v6 00/11] Add support for ast2600 ADC Billy Tsai
2021-09-13 7:53 ` [v6 01/11] iio: adc: aspeed: Keep model data to driver data Billy Tsai
2021-09-13 7:53 ` [v6 02/11] iio: adc: aspeed: Restructure the model data Billy Tsai
2021-09-13 7:53 ` [v6 03/11] iio: adc: aspeed: Add vref config function Billy Tsai
2021-09-13 7:53 ` [v6 04/11] iio: adc: aspeed: Use model_data to set clk scaler Billy Tsai
2021-09-13 7:53 ` [v6 05/11] iio: adc: aspeed: Use devm_add_action_or_reset Billy Tsai
2021-09-13 7:53 ` [v6 06/11] iio: adc: aspeed: Support ast2600 adc Billy Tsai
2021-09-13 7:53 ` [v6 07/11] iio: adc: aspeed: Fix the calculate error of clock Billy Tsai
2021-09-17 1:12 ` Billy Tsai
2021-09-18 17:57 ` Jonathan Cameron
2021-09-13 7:53 ` Billy Tsai [this message]
2021-09-13 7:53 ` [v6 09/11] iio: adc: aspeed: Add compensation phase Billy Tsai
2021-09-13 7:53 ` [v6 10/11] iio: adc: aspeed: Support battery sensing Billy Tsai
2021-09-13 7:53 ` [v6 11/11] iio: adc: aspeed: Get and set trimming data Billy Tsai
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