[PATCH 0/3] net: macb: add support for MII on RGMII interface

[PATCH 0/3] net: macb: add support for MII on RGMII interface

[Claudiu Beznea]

Hi,

This series adds support for MII mode on RGMII interface (patch 3/3).
Along with this the series also contains minor cleanups (patches 1/3, 2/3)
on macb.h.

Thank you,
Claudiu Beznea

Claudiu Beznea (3):
  net: macb: add description for SRTSM
  net: macb: align for OSSMODE offset
  net: macb: add support for mii on rgmii

 drivers/net/ethernet/cadence/macb.h      | 7 +++++--
 drivers/net/ethernet/cadence/macb_main.c | 3 +++
 2 files changed, 8 insertions(+), 2 deletions(-)

-- 
2.25.1

[PATCH 1/3] net: macb: add description for SRTSM

[Claudiu Beznea]

Add description for SRTSM bit.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/net/ethernet/cadence/macb.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index d8d87213697c..d1e0e116b976 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -243,7 +243,7 @@
 #define MACB_NCR_TPF_SIZE	1
 #define MACB_TZQ_OFFSET		12 /* Transmit zero quantum pause frame */
 #define MACB_TZQ_SIZE		1
-#define MACB_SRTSM_OFFSET	15
+#define MACB_SRTSM_OFFSET	15 /* Store Receive Timestamp to Memory */
 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
 #define MACB_OSSMODE_SIZE	1
 
-- 
2.25.1

[PATCH 2/3] net: macb: align for OSSMODE offset

[Claudiu Beznea]

Align for OSSMODE offset.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/net/ethernet/cadence/macb.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index d1e0e116b976..c33e98bfa5e8 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -244,7 +244,7 @@
 #define MACB_TZQ_OFFSET		12 /* Transmit zero quantum pause frame */
 #define MACB_TZQ_SIZE		1
 #define MACB_SRTSM_OFFSET	15 /* Store Receive Timestamp to Memory */
-#define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
+#define MACB_OSSMODE_OFFSET	24 /* Enable One Step Synchro Mode */
 #define MACB_OSSMODE_SIZE	1
 
 /* Bitfields in NCFGR */
-- 
2.25.1

[PATCH 3/3] net: macb: add support for mii on rgmii

[Claudiu Beznea]

Cadence IP has option to enable MII support on RGMII interface. This
could be selected though bit 28 of network control register. This option
is not enabled on all the IP versions thus add a software capability to
be selected by the proper implementation of this IP.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/net/ethernet/cadence/macb.h      | 3 +++
 drivers/net/ethernet/cadence/macb_main.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index c33e98bfa5e8..5620b97b3482 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -246,6 +246,8 @@
 #define MACB_SRTSM_OFFSET	15 /* Store Receive Timestamp to Memory */
 #define MACB_OSSMODE_OFFSET	24 /* Enable One Step Synchro Mode */
 #define MACB_OSSMODE_SIZE	1
+#define MACB_MIIONRGMII_OFFSET	28 /* MII Usage on RGMII Interface */
+#define MACB_MIIONRGMII_SIZE	1
 
 /* Bitfields in NCFGR */
 #define MACB_SPD_OFFSET		0 /* Speed */
@@ -713,6 +715,7 @@
 #define MACB_CAPS_GEM_HAS_PTP			0x00000040
 #define MACB_CAPS_BD_RD_PREFETCH		0x00000080
 #define MACB_CAPS_NEEDS_RSTONUBR		0x00000100
+#define MACB_CAPS_MIIONRGMII			0x00000200
 #define MACB_CAPS_CLK_HW_CHG			0x04000000
 #define MACB_CAPS_MACB_IS_EMAC			0x08000000
 #define MACB_CAPS_FIFO_MODE			0x10000000
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index d13fb1d31821..cdf3e35b5b33 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -684,6 +684,9 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode,
 		} else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
 			ctrl |= GEM_BIT(PCSSEL);
 			ncr |= GEM_BIT(ENABLE_HS_MAC);
+		} else if (bp->caps & MACB_CAPS_MIIONRGMII &&
+			   bp->phy_interface == PHY_INTERFACE_MODE_MII) {
+			ncr |= MACB_BIT(MIIONRGMII);
 		}
 	}
 
-- 
2.25.1

Re: [PATCH 2/3] net: macb: align for OSSMODE offset

[Nicolas.Ferre]

On 15/09/2021 at 08:47, Claudiu Beznea wrote:
> Align for OSSMODE offset.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> ---
>   drivers/net/ethernet/cadence/macb.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index d1e0e116b976..c33e98bfa5e8 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -244,7 +244,7 @@
>   #define MACB_TZQ_OFFSET		12 /* Transmit zero quantum pause frame */
>   #define MACB_TZQ_SIZE		1
>   #define MACB_SRTSM_OFFSET	15 /* Store Receive Timestamp to Memory */
> -#define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
> +#define MACB_OSSMODE_OFFSET	24 /* Enable One Step Synchro Mode */
>   #define MACB_OSSMODE_SIZE	1
>   
>   /* Bitfields in NCFGR */
> 


-- 
Nicolas Ferre

Re: [PATCH 3/3] net: macb: add support for mii on rgmii

[Nicolas.Ferre]

On 15/09/2021 at 08:47, Claudiu Beznea wrote:
> Cadence IP has option to enable MII support on RGMII interface. This
> could be selected though bit 28 of network control register. This option
> is not enabled on all the IP versions thus add a software capability to
> be selected by the proper implementation of this IP.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Fine:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

Thanks Claudiu, best regards,
   Nicolas

> ---
>   drivers/net/ethernet/cadence/macb.h      | 3 +++
>   drivers/net/ethernet/cadence/macb_main.c | 3 +++
>   2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index c33e98bfa5e8..5620b97b3482 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -246,6 +246,8 @@
>   #define MACB_SRTSM_OFFSET	15 /* Store Receive Timestamp to Memory */
>   #define MACB_OSSMODE_OFFSET	24 /* Enable One Step Synchro Mode */
>   #define MACB_OSSMODE_SIZE	1
> +#define MACB_MIIONRGMII_OFFSET	28 /* MII Usage on RGMII Interface */
> +#define MACB_MIIONRGMII_SIZE	1
>   
>   /* Bitfields in NCFGR */
>   #define MACB_SPD_OFFSET		0 /* Speed */
> @@ -713,6 +715,7 @@
>   #define MACB_CAPS_GEM_HAS_PTP			0x00000040
>   #define MACB_CAPS_BD_RD_PREFETCH		0x00000080
>   #define MACB_CAPS_NEEDS_RSTONUBR		0x00000100
> +#define MACB_CAPS_MIIONRGMII			0x00000200
>   #define MACB_CAPS_CLK_HW_CHG			0x04000000
>   #define MACB_CAPS_MACB_IS_EMAC			0x08000000
>   #define MACB_CAPS_FIFO_MODE			0x10000000
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index d13fb1d31821..cdf3e35b5b33 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -684,6 +684,9 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode,
>   		} else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
>   			ctrl |= GEM_BIT(PCSSEL);
>   			ncr |= GEM_BIT(ENABLE_HS_MAC);
> +		} else if (bp->caps & MACB_CAPS_MIIONRGMII &&
> +			   bp->phy_interface == PHY_INTERFACE_MODE_MII) {
> +			ncr |= MACB_BIT(MIIONRGMII);
>   		}
>   	}
>   
> 


-- 
Nicolas Ferre

Re: [PATCH 1/3] net: macb: add description for SRTSM

[Nicolas.Ferre]

On 15/09/2021 at 08:47, Claudiu Beznea wrote:
> Add description for SRTSM bit.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> ---
>   drivers/net/ethernet/cadence/macb.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
> index d8d87213697c..d1e0e116b976 100644
> --- a/drivers/net/ethernet/cadence/macb.h
> +++ b/drivers/net/ethernet/cadence/macb.h
> @@ -243,7 +243,7 @@
>   #define MACB_NCR_TPF_SIZE	1
>   #define MACB_TZQ_OFFSET		12 /* Transmit zero quantum pause frame */
>   #define MACB_TZQ_SIZE		1
> -#define MACB_SRTSM_OFFSET	15
> +#define MACB_SRTSM_OFFSET	15 /* Store Receive Timestamp to Memory */
>   #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
>   #define MACB_OSSMODE_SIZE	1
>   
> 


-- 
Nicolas Ferre

Re: [PATCH 3/3] net: macb: add support for mii on rgmii

[Andrew Lunn]

On Wed, Sep 15, 2021 at 09:47:21AM +0300, Claudiu Beznea wrote:
> Cadence IP has option to enable MII support on RGMII interface. This
> could be selected though bit 28 of network control register. This option
> is not enabled on all the IP versions thus add a software capability to
> be selected by the proper implementation of this IP.

Hi Claudiu

You are adding a feature without a user. That is generally not
accepted. Could you please also extend one of the macb_config structs
to make use of this?

Thanks
	Andrew

Re: [PATCH 3/3] net: macb: add support for mii on rgmii

[Claudiu.Beznea]

Hi Andrew,

On 16.09.2021 16:03, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Wed, Sep 15, 2021 at 09:47:21AM +0300, Claudiu Beznea wrote:
>> Cadence IP has option to enable MII support on RGMII interface. This
>> could be selected though bit 28 of network control register. This option
>> is not enabled on all the IP versions thus add a software capability to
>> be selected by the proper implementation of this IP.
> 
> Hi Claudiu
> 
> You are adding a feature without a user. That is generally not
> accepted.

That's true. For whatever reason I haven't added proper flags to
macb_config objects. I've send a new version with updates.

Thank you for your review,
Claudiu Beznea

> Could you please also extend one of the macb_config structs
> to make use of this?
> 
> Thanks
>         Andrew
>