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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v2 02/21] x86/msr: add AMD CPPC MSR definitions Date: Sun, 26 Sep 2021 17:05:46 +0800 Message-ID: <20210926090605.3556134-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210926090605.3556134-1-ray.huang@amd.com> References: <20210926090605.3556134-1-ray.huang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8695953f-0679-4985-7a2a-08d980ccec02 X-MS-TrafficTypeDiagnostic: BYAPR12MB3512: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lwN+9ZDSW0ACFB2ItfTY+54nNLh2IhXs0EN5/tXlDvYGuyW3gqHtICiHyRVFYfkQMHqBmFwaYeQdSzXkb7eTvjqAmuisEg/HU+vdI9SBzhnnxzXhG/Oo/IutwwQSE2Tb/pPp4dv1Sp64n4MZDzVhzCIfub9K26JdMlBZWMcidERkywg3MLOmVNDi4VpgYqh9Ptb5PlkiiC0hVjUMoEC/01JiScy4yhasfcPCe1rXN+pvQTkvzbjTiff8me2G+HH+inqxcHRkKyTVwhIm+apyQPcE4/ThUlq1E7tchByWbePgcKSB6sVCpqLtWZeRQRgeyLS86Snpmt+eiEXN0HNO6HvO26wU0ZoM0RhB7TqDT4MGHvQEcR6W+IM9dHuqqKu0sWs4KmM+7H+WCx2VqCLqRb6TN/I69tsg/AkB586sjSddsUFvy9HWhfjzVaw+87piotkbwmec2AVHh3mo/Gm0dqEoiUW5zJTij5YG5StVRO8yYLKc9jix1wnObBD9LbsiRoe6lXjsc24SvrHbVsJNY85UzBltxfJ/yvWU7krk/RIQxjtrYSQ++DtozJ4Pf9o3BH/fw+LdNpr4yCD/Er4IT/dlByV/JiuKKEbmkUInc3p8j28HUm7Lel6gIwJnoAgU9VtjJyZ/0PtusSTmpCZ1ENmQYq6+t2tfEY+nHLbd1j7u+Ov6BD9MgaDqzQ1KCeZ314JDKc6ZKyHFrTDYe+V9AbtLt8jXwVWVwS0+GJWmcds= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(54906003)(110136005)(8936002)(8676002)(316002)(4326008)(36860700001)(82310400003)(47076005)(36756003)(356005)(2906002)(81166007)(86362001)(26005)(336012)(508600001)(6666004)(16526019)(186003)(70586007)(5660300002)(2616005)(426003)(70206006)(1076003)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2021 09:06:26.9295 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8695953f-0679-4985-7a2a-08d980ccec02 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3512 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a7c413432b33..ce42e15cf303 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,23 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* AMD Collaborative Processor Performance Control MSRs */ +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define MSR_AMD_CPPC_CAP2 0xc00102b2 +#define MSR_AMD_CPPC_REQ 0xc00102b3 +#define MSR_AMD_CPPC_STATUS 0xc00102b4 + +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff) +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff) +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff) + +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0) +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8) +#define REQ_DES_PERF(x) (((x) & 0xff) << 16) +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 -- 2.25.1