From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C670C433EF for ; Thu, 30 Sep 2021 15:25:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3635961A2C for ; Thu, 30 Sep 2021 15:25:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343646AbhI3P0z (ORCPT ); Thu, 30 Sep 2021 11:26:55 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52420 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231637AbhI3P0y (ORCPT ); Thu, 30 Sep 2021 11:26:54 -0400 X-UUID: 9d8a817538964c64b921d86f966a1009-20210930 X-UUID: 9d8a817538964c64b921d86f966a1009-20210930 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 836598912; Thu, 30 Sep 2021 23:25:08 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Sep 2021 23:25:07 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Sep 2021 23:25:06 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Sep 2021 23:25:05 +0800 From: Yongqiang Niu To: Chun-Kuang Hu CC: Rob Herring , Matthias Brugger , Philipp Zabel , "David Airlie" , Daniel Vetter , Jassi Brar , Yongqiang Niu , Fabien Parent , Dennis YC Hsieh , , , , , , , Hsin-Yi Wang Subject: [PATCHi v6, 1/1] drm/mediatek: add dither 6 setting Date: Thu, 30 Sep 2021 23:25:06 +0800 Message-ID: <20210930152506.12086-2-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210930152506.12086-1-yongqiang.niu@mediatek.com> References: <20210930152506.12086-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org dither 6 setting is missed in a6b7c98afdca bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable bit 2 is rdither_en(Enables running order dithering), need disable Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common()) Signed-off-by: Yongqiang Niu Change-Id: I30258dd4129d17fb7d94b1714d78bc133e88338e --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 99cbf44463e4..33e8789fde8a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -26,6 +26,8 @@ #define DISP_OD_CFG 0x0020 #define DISP_OD_SIZE 0x0030 #define DISP_DITHER_5 0x0114 +#define DISP_DITHER_6 0x0118 +#define LFSR_EN BIT(1) #define DISP_DITHER_7 0x011c #define DISP_DITHER_15 0x013c #define DISP_DITHER_16 0x0140 @@ -135,6 +137,7 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, if (bpc >= MTK_MIN_BPC) { mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5); + mtk_ddp_write_mask(cmdq_pkt, LFSR_EN, cmdq_reg, regs, DISP_DITHER_6, LFSR_EN); mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | -- 2.25.1