From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Andrzej Hajda <a.hajda@samsung.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Robert Foss <robert.foss@linaro.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Jonas Karlman <jonas@kwiboo.se>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Maxim Schwalm <maxim.schwalm@gmail.com>,
Andreas Westman Dorcsak <hedmoo@yahoo.com>,
Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v1 2/5] drm/bridge: tc358768: Support pulse mode
Date: Sun, 3 Oct 2021 02:34:44 +0300 [thread overview]
Message-ID: <20211002233447.1105-3-digetx@gmail.com> (raw)
In-Reply-To: <20211002233447.1105-1-digetx@gmail.com>
Support pulse-mode synchronization which is supported and used by simple
DSI panels like Panasonic VVX10F004B00.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # Asus TF700T
Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> #TF700T
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/gpu/drm/bridge/tc358768.c | 66 ++++++++++++++++++++++---------
1 file changed, 48 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
index 18ae6605a803..10ebd0621ad3 100644
--- a/drivers/gpu/drm/bridge/tc358768.c
+++ b/drivers/gpu/drm/bridge/tc358768.c
@@ -785,24 +785,54 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
/* START[0] */
tc358768_write(priv, TC358768_STARTCNTRL, 1);
- /* Set event mode */
- tc358768_write(priv, TC358768_DSI_EVENT, 1);
-
- /* vsw (+ vbp) */
- tc358768_write(priv, TC358768_DSI_VSW,
- mode->vtotal - mode->vsync_start);
- /* vbp (not used in event mode) */
- tc358768_write(priv, TC358768_DSI_VBPR, 0);
- /* vact */
- tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
-
- /* (hsw + hbp) * byteclk * ndl / pclk */
- val = (u32)div_u64((mode->htotal - mode->hsync_start) *
- ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
- mode->clock * 1000);
- tc358768_write(priv, TC358768_DSI_HSW, val);
- /* hbp (not used in event mode) */
- tc358768_write(priv, TC358768_DSI_HBPR, 0);
+ if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
+ /* Set pulse mode */
+ tc358768_write(priv, TC358768_DSI_EVENT, 0);
+
+ /* vact */
+ tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
+
+ /* vsw */
+ tc358768_write(priv, TC358768_DSI_VSW,
+ mode->vsync_end - mode->vsync_start);
+ /* vbp */
+ tc358768_write(priv, TC358768_DSI_VBPR,
+ mode->vtotal - mode->vsync_end);
+
+ /* hsw * byteclk * ndl / pclk */
+ val = (u32)div_u64((mode->hsync_end - mode->hsync_start) *
+ ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
+ mode->clock * 1000);
+ tc358768_write(priv, TC358768_DSI_HSW, val);
+
+ /* hbp * byteclk * ndl / pclk */
+ val = (u32)div_u64((mode->htotal - mode->hsync_end) *
+ ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
+ mode->clock * 1000);
+ tc358768_write(priv, TC358768_DSI_HBPR, val);
+ } else {
+ /* Set event mode */
+ tc358768_write(priv, TC358768_DSI_EVENT, 1);
+
+ /* vact */
+ tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
+
+ /* vsw (+ vbp) */
+ tc358768_write(priv, TC358768_DSI_VSW,
+ mode->vtotal - mode->vsync_start);
+ /* vbp (not used in event mode) */
+ tc358768_write(priv, TC358768_DSI_VBPR, 0);
+
+ /* (hsw + hbp) * byteclk * ndl / pclk */
+ val = (u32)div_u64((mode->htotal - mode->hsync_start) *
+ ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
+ mode->clock * 1000);
+ tc358768_write(priv, TC358768_DSI_HSW, val);
+
+ /* hbp (not used in event mode) */
+ tc358768_write(priv, TC358768_DSI_HBPR, 0);
+ }
+
/* hact (bytes) */
tc358768_write(priv, TC358768_DSI_HACT, hact);
--
2.32.0
next prev parent reply other threads:[~2021-10-02 23:35 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-02 23:34 [PATCH v1 0/5] Improvements for TC358768 DSI bridge driver Dmitry Osipenko
2021-10-02 23:34 ` [PATCH v1 1/5] drm/bridge: tc358768: Enable reference clock Dmitry Osipenko
2021-10-19 8:47 ` Robert Foss
2021-10-02 23:34 ` Dmitry Osipenko [this message]
2021-10-19 8:55 ` [PATCH v1 2/5] drm/bridge: tc358768: Support pulse mode Robert Foss
2021-10-02 23:34 ` [PATCH v1 3/5] drm/bridge: tc358768: Calculate video start delay Dmitry Osipenko
2021-10-19 9:27 ` Robert Foss
2021-10-02 23:34 ` [PATCH v1 4/5] drm/bridge: tc358768: Disable non-continuous clock mode Dmitry Osipenko
2021-10-19 9:37 ` Robert Foss
2021-10-02 23:34 ` [PATCH v1 5/5] drm/bridge: tc358768: Correct BTACNTRL1 programming Dmitry Osipenko
2021-10-19 9:38 ` Robert Foss
2021-10-19 9:47 ` [PATCH v1 0/5] Improvements for TC358768 DSI bridge driver Robert Foss
2021-10-19 20:37 ` Dmitry Osipenko
2021-12-19 16:02 ` Dmitry Osipenko
2021-12-21 18:10 ` Robert Foss
2021-12-21 18:15 ` Dmitry Osipenko
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