From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5F3FC4332F for ; Sun, 3 Oct 2021 08:33:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE6BD61350 for ; Sun, 3 Oct 2021 08:33:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230045AbhJCIfS (ORCPT ); Sun, 3 Oct 2021 04:35:18 -0400 Received: from mail.z3ntu.xyz ([128.199.32.197]:37968 "EHLO mail.z3ntu.xyz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229951AbhJCIdy (ORCPT ); Sun, 3 Oct 2021 04:33:54 -0400 Received: from g550jk.portal.nstrein.ns.nl (unknown [145.15.244.215]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id E8C92C9101; Sun, 3 Oct 2021 08:32:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=z3ntu.xyz; s=z3ntu; t=1633249926; bh=HG/XwGTM9gGLxOPy8XHZzg4WGcWzyHdCYnENX4HY7Wo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=gj/VDxYetLLRvgYF3jMILDN8F10iV3/NoG3O1heTtkttP58FnnI7d+1ZtrG33DNK2 njL13YsvrAIFdvjifPPG7JybdAXLV09wOWWwc9UjT2dulJs+dRNoDbJje5S6Bj6Jh2 JvF/F+LawSjymuYLdR7JDxP4E5vZwxb0mxAtBt98= From: Luca Weiss To: linux-arm-msm@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, Luca Weiss , Andy Gross , Bjorn Andersson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/11] arm64: dts: qcom: sm6350: add debug uart Date: Sun, 3 Oct 2021 10:31:30 +0200 Message-Id: <20211003083141.613509-8-luca@z3ntu.xyz> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211003083141.613509-1-luca@z3ntu.xyz> References: <20211003083141.613509-1-luca@z3ntu.xyz> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the necessary nodes for the debug uart on SM6350. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 95e69d9f8657..630a76e740f8 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -445,6 +445,30 @@ opp-384000000 { }; }; + qupv3_id_1: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu 0x4c3 0x0>; + ranges; + status = "disabled"; + + uart2: serial@98c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x98c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart2_default>; + interrupts = ; + status = "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -672,6 +696,13 @@ tlmm: pinctrl@f100000 { interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; + + qup_uart2_default: qup-uart2-default { + mux { + pins = "gpio25", "gpio26"; + function = "qup13_f2"; + }; + }; }; apps_smmu: iommu@15000000 { -- 2.33.0