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[73.25.156.94]) by smtp.gmail.com with ESMTPSA id e1sm18677200pgi.43.2021.10.05.08.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Oct 2021 08:12:01 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, Jordan Crouse , Robin Murphy , Will Deacon , Rob Clark , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Akhil P Oommen , Jonathan Marek , Sai Prakash Ranjan , Sharat Masetty , Douglas Anderson , =?UTF-8?q?Christian=20K=C3=B6nig?= , Yangtao Li , Konrad Dybcio , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 2/3] drm/msm: Show all smmu info for iova fault devcore dumps Date: Tue, 5 Oct 2021 08:16:26 -0700 Message-Id: <20211005151633.1738878-3-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211005151633.1738878-1-robdclark@gmail.com> References: <20211005151633.1738878-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rob Clark Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 25 +++++++++++++++++-------- drivers/gpu/drm/msm/msm_gpu.h | 2 +- 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 34fede935ac0..96e0ca986c54 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1282,7 +1282,7 @@ static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *da /* Turn off the hangcheck timer to keep it from bothering us */ del_timer(&gpu->hangcheck_timer); - gpu->fault_info.ttbr0 = info->ttbr0; + gpu->fault_info.smmu_info = *info; gpu->fault_info.iova = iova; gpu->fault_info.flags = flags; gpu->fault_info.type = type; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 748665232d29..42e522a60623 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -685,19 +685,28 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, adreno_gpu->rev.major, adreno_gpu->rev.minor, adreno_gpu->rev.patchid); /* - * If this is state collected due to iova fault, so fault related info + * If this is state collected due to iova fault, show fault related + * info * - * TTBR0 would not be zero, so this is a good way to distinguish + * TTBR0 would not be zero in this case, so this is a good way to + * distinguish */ - if (state->fault_info.ttbr0) { + if (state->fault_info.smmu_info.ttbr0) { const struct msm_gpu_fault_info *info = &state->fault_info; + const struct adreno_smmu_fault_info *smmu_info = &info->smmu_info; drm_puts(p, "fault-info:\n"); - drm_printf(p, " - ttbr0=%.16llx\n", info->ttbr0); - drm_printf(p, " - iova=%.16lx\n", info->iova); - drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ"); - drm_printf(p, " - type=%s\n", info->type); - drm_printf(p, " - source=%s\n", info->block); + drm_printf(p, " - far: %.16llx\n", smmu_info->far); + drm_printf(p, " - ttbr0: %.16llx\n", smmu_info->ttbr0); + drm_printf(p, " - contextidr: %.8x\n", smmu_info->contextidr); + drm_printf(p, " - fsr: %.8x\n", smmu_info->fsr); + drm_printf(p, " - fsynr0: %.8x\n", smmu_info->fsynr0); + drm_printf(p, " - fsynr1: %.8x\n", smmu_info->fsynr1); + drm_printf(p, " - cbfrsynra: %.8x\n", smmu_info->cbfrsynra); + drm_printf(p, " - iova: %.16lx\n", info->iova); + drm_printf(p, " - dir: %s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ"); + drm_printf(p, " - type: %s\n", info->type); + drm_printf(p, " - source: %s\n", info->block); } drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 9801a965816c..0e132795123f 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -73,7 +73,7 @@ struct msm_gpu_funcs { /* Additional state for iommu faults: */ struct msm_gpu_fault_info { - u64 ttbr0; + struct adreno_smmu_fault_info smmu_info; unsigned long iova; int flags; const char *type; -- 2.31.1