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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id q2sm2685808pjo.27.2021.10.05.10.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Oct 2021 10:04:34 -0700 (PDT) Date: Tue, 5 Oct 2021 11:04:32 -0600 From: Mathieu Poirier To: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, anshuman.khandual@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org Subject: Re: [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Message-ID: <20211005170432.GB3311227@p14s> References: <20210921134121.2423546-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210921134121.2423546-1-suzuki.poulose@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 21, 2021 at 02:41:04PM +0100, Suzuki K Poulose wrote: > This series adds CPU erratum work arounds related to the self-hosted > tracing. The list of affected errata handled in this series are : > > * TRBE may overwrite trace in FILL mode > - Arm Neoverse-N2 #2139208 > - Cortex-A710 #211985 > > * A TSB instruction may not flush the trace completely when executed > in trace prohibited region. > > - Arm Neoverse-N2 #2067961 > - Cortex-A710 #2054223 > > * TRBE may write to out-of-range address > - Arm Neoverse-N2 #2253138 > - Cortex-A710 #2224489 > > The series applies on the self-hosted/trbe fixes posted here [0]. > A tree containing both the series is available here [1] > > [0] https://lkml.kernel.org/r/20210914102641.1852544-1-suzuki.poulose@arm.com > [1] git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v2 > > Changes since v1: > https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com > - Added a fix to the TRBE driver handling of sink_specific data > - Added more description and ASCII art for overwrite in FILL mode > work around > - Added another TRBE erratum to the list. > "TRBE may write to out-of-range address" > Patches from 12-17 > - Added comment to list the expectations around TSB erratum workaround. > > > Suzuki K Poulose (17): > coresight: trbe: Fix incorrect access of the sink specific data > coresight: trbe: Add infrastructure for Errata handling > coresight: trbe: Add a helper to calculate the trace generated > coresight: trbe: Add a helper to pad a given buffer area > coresight: trbe: Decouple buffer base from the hardware base > coresight: trbe: Allow driver to choose a different alignment > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > arm64: Add erratum detection for TRBE overwrite in FILL mode > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > arm64: Enable workaround for TRBE overwrite in FILL mode > arm64: errata: Add workaround for TSB flush failures > coresight: trbe: Add a helper to fetch cpudata from perf handle > coresight: trbe: Add a helper to determine the minimum buffer size > coresight: trbe: Make sure we have enough space > arm64: Add erratum detection for TRBE write to out-of-range > coresight: trbe: Work around write to out of range > arm64: Advertise TRBE erratum workaround for write to out-of-range address > > Documentation/arm64/silicon-errata.rst | 12 + > arch/arm64/Kconfig | 109 ++++++ > arch/arm64/include/asm/barrier.h | 16 +- > arch/arm64/include/asm/cputype.h | 4 + > arch/arm64/kernel/cpu_errata.c | 64 ++++ > arch/arm64/tools/cpucaps | 3 + > drivers/hwtracing/coresight/coresight-trbe.c | 339 +++++++++++++++++-- > 7 files changed, 510 insertions(+), 37 deletions(-) Patches 04 to 11 and 13 to 17: Reviewed-by: Mathieu Poirier I am done reviewing this set. Thanks, Mathieu > > -- > 2.24.1 >