Re: Re: [PATCH] arm64: traps: add dump instr before BUG in kernel

From: Will Deacon <will@kernel.org>
To: Chen Lin <chen45464546@163.com>
Cc: catalin.marinas@arm.com, mark.rutland@arm.com,
	joey.gouly@arm.com, maz@kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, chen.lin5@zte.com.cn
Subject: Re: Re: [PATCH] arm64: traps: add dump instr before BUG in kernel
Date: Mon, 11 Oct 2021 11:06:50 +0100	[thread overview]
Message-ID: <20211011100649.GB3681@willie-the-truck> (raw)
In-Reply-To: <1633012890-3118-1-git-send-email-chen45464546@163.com>

On Thu, Sep 30, 2021 at 10:41:30PM +0800, Chen Lin wrote:
> At 2021-09-30 15:42:47, "Will Deacon" <will@kernel.org> wrote:
> 
> >On Wed, Sep 29, 2021 at 09:29:46PM +0800, Chen Lin wrote:
> >> From: Chen Lin <chen.lin5@zte.com.cn>
> >> 
> >> we should dump the real instructions before BUG in kernel mode, and
> >> compare this to the instructions from objdump.
> >> 
> >> Signed-off-by: Chen Lin <chen.lin5@zte.com.cn>
> >> ---
> >>  arch/arm64/kernel/traps.c |    7 ++++++-
> >>  1 file changed, 6 insertions(+), 1 deletion(-)
> >> 
> >> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
> >> index b03e383..621a9dd 100644
> >> --- a/arch/arm64/kernel/traps.c
> >> +++ b/arch/arm64/kernel/traps.c
> >> @@ -495,7 +495,12 @@ void do_undefinstr(struct pt_regs *regs)
> >>  	if (call_undef_hook(regs) == 0)
> >>  		return;
> >>  
> >> -	BUG_ON(!user_mode(regs));
> >> +	if (!user_mode(regs)) {
> >> +		pr_emerg("Undef instruction in kernel, dump instr:");
> >> +		dump_kernel_instr(KERN_EMERG, regs);
> >> +		BUG();
> >> +	}
> >
> >Hmm, I'm not completely convinced about this as the instruction in the
> >i-cache could be completely different. I think the PC value (for addr2line)
> >is a lot more useful, and we should be printing that already.
> >
> >Maybe you can elaborate on a situation where this information was helpful?
> >
> >Thanks,
> >
> >Will
> 
> Undef instruction occurs in some cases
> 
> 1. CPU do not have the permission to execute the instruction or the current CPU
>  version does not support the instruction. For example, execute 
>  'mrs x0, tcr_el3' under el1.

This really shouldn't happen, but if it did, the PC would surely be enough
to debug the problem?

> 2. The instruction is a normal instruction, but it is changed during board 
> running in some abnormal situation. eg: DDR bit flip, the normal instruction 
> will become an undefined one. By printing the instruction, we can see the 
> accurate instruction code and compare it with the instruction code from objdump
> to determine that it is a DDR issue.

Is this really something we should be designing our exception handlers for?
If we're getting DDR bit flips for kernel .text, then it sounds like we need
ECC and/or RAS features to deal with them.

So I'm not really sold on this change.

Will