From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: will@kernel.org, mathieu.poirier@linaro.org
Cc: catalin.marinas@arm.com, anshuman.khandual@arm.com,
mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH v4 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
Date: Tue, 12 Oct 2021 14:17:29 +0100 [thread overview]
Message-ID: <20211012131743.2040596-2-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20211012131743.2040596-1-suzuki.poulose@arm.com>
Add the CPU Partnumbers for the new Arm designs.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/cputype.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 6231e1f0abe7..19b8441aa8f2 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -73,6 +73,8 @@
#define ARM_CPU_PART_CORTEX_A76 0xD0B
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
#define ARM_CPU_PART_CORTEX_A77 0xD0D
+#define ARM_CPU_PART_CORTEX_A710 0xD47
+#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define APM_CPU_PART_POTENZA 0x000
@@ -113,6 +115,8 @@
#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
+#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
+#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
--
2.25.4
next prev parent reply other threads:[~2021-10-12 13:18 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-12 13:17 [PATCH v4 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-10-12 13:17 ` Suzuki K Poulose [this message]
2021-10-12 13:17 ` [PATCH v4 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-12 15:31 ` Randy Dunlap
2021-10-14 14:17 ` Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose
2021-10-12 15:35 ` Randy Dunlap
2021-10-12 13:17 ` [PATCH v4 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 08/15] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-12 13:17 ` [PATCH v4 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose
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