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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id k16sm1033761lfo.219.2021.10.12.06.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 06:42:16 -0700 (PDT) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org Cc: Emil Renner Berthing , Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Linus Walleij , Greg Kroah-Hartman , Daniel Lezcano , Andy Shevchenko , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Geert Uytterhoeven , Anup Patel , Atish Patra , Matteo Croce , linux-kernel@vger.kernel.org Subject: [PATCH v1 14/16] serial: 8250_dw: Add skip_clk_set_rate quirk Date: Tue, 12 Oct 2021 15:40:25 +0200 Message-Id: <20211012134027.684712-15-kernel@esmil.dk> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211012134027.684712-1-kernel@esmil.dk> References: <20211012134027.684712-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On the StarFive JH7100 SoC the uart core clocks can't be set to exactly 16 * 115200Hz and many other common bitrates. Trying this will only result in a higher input clock, but low enough that the uart's internal divisor can't come close enough to the baud rate target. So rather than try to set the input clock it's better to rely solely on the uart's internal divisor. Signed-off-by: Emil Renner Berthing --- drivers/tty/serial/8250/8250_dw.c | 32 ++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index a3a0154da567..dee26c0909fd 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -51,6 +51,7 @@ struct dw8250_data { unsigned int skip_autocfg:1; unsigned int uart_16550_compatible:1; + unsigned int skip_clk_set_rate:1; }; static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) @@ -334,21 +335,23 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, long rate; int ret; - clk_disable_unprepare(d->clk); - rate = clk_round_rate(d->clk, newrate); - if (rate > 0) { - /* - * Premilinary set the uartclk to the new clock rate so the - * clock update event handler caused by the clk_set_rate() - * calling wouldn't actually update the UART divisor since - * we about to do this anyway. - */ - swap(p->uartclk, rate); - ret = clk_set_rate(d->clk, newrate); - if (ret) + if (!d->skip_clk_set_rate) { + clk_disable_unprepare(d->clk); + rate = clk_round_rate(d->clk, newrate); + if (rate > 0) { + /* + * Premilinary set the uartclk to the new clock rate so + * the clock update event handler caused by the + * clk_set_rate() calling wouldn't actually update the + * UART divisor since we about to do this anyway. + */ swap(p->uartclk, rate); + ret = clk_set_rate(d->clk, newrate); + if (ret) + swap(p->uartclk, rate); + } + clk_prepare_enable(d->clk); } - clk_prepare_enable(d->clk); p->status &= ~UPSTAT_AUTOCTS; if (termios->c_cflag & CRTSCTS) @@ -418,6 +421,8 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) } if (of_device_is_compatible(np, "marvell,armada-38x-uart")) p->serial_out = dw8250_serial_out38x; + if (of_device_is_compatible(np, "starfive,jh7100-uart")) + data->skip_clk_set_rate = true; } else if (acpi_dev_present("APMC0D08", NULL, -1)) { p->iotype = UPIO_MEM32; @@ -700,6 +705,7 @@ static const struct of_device_id dw8250_of_match[] = { { .compatible = "cavium,octeon-3860-uart" }, { .compatible = "marvell,armada-38x-uart" }, { .compatible = "renesas,rzn1-uart" }, + { .compatible = "starfive,jh7100-uart" }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dw8250_of_match); -- 2.33.0