From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F269C433F5 for ; Wed, 13 Oct 2021 01:22:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F060760F21 for ; Wed, 13 Oct 2021 01:22:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236268AbhJMBYS (ORCPT ); Tue, 12 Oct 2021 21:24:18 -0400 Received: from mail.kernel.org ([198.145.29.99]:54448 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234055AbhJMBYR (ORCPT ); Tue, 12 Oct 2021 21:24:17 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id C89E9604D2; Wed, 13 Oct 2021 01:22:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634088134; bh=468WHYFwB6WFDhp8ouf1HntwGAoFETGsz8CZghL0FKA=; h=From:To:Cc:Subject:Date:From; b=RipuErGRqkVoqnXnfk2l6WgyfFMaVtMuXqOttmm6D+0kKavAT52ABC0etQyzNjgyj JSxsnhtFdw1+hhaZ4bymhMhOCm6f9UTF0usrkdWXRIK4apJqIOmoTAgcCXAS6Yq26l PSBCYz4lkApVimpSVFjTfzfxyxaO9x9kp4eIOvM8Q7yewxah0C9+D1oVEMsd+5IjRt NmFF4/Ls5tFKlwuuaHepTgzLOdJJkIa6+mKyOR0ajiFPhqHfICP61mxRt5eDuLiD8k LsztBiHuHLwQv6oC/d2u1YPM6ONg+QLTAu3Q0D2BSTxkDPtGQhILppNv22gdFxGTSj b17srNpQqGwqA== From: guoren@kernel.org To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Rob Herring , Palmer Dabbelt Subject: [PATCH V3 1/2] dt-bindings: update riscv plic compatible string Date: Wed, 13 Oct 2021 09:21:48 +0800 Message-Id: <20211013012149.2834212-1-guoren@kernel.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Guo Ren Add the compatible string "thead,c900-plic" to the riscv plic bindings to support SOCs with thead,c9xx processor cores. Signed-off-by: Guo Ren Cc: Rob Herring Cc: Palmer Dabbelt Cc: Anup Patel Cc: Atish Patra --- Changes since V3: - Rename "c9xx" to "c900" - Add thead,c900-plic in the description section --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 08d5a57ce00f..82629832e5a5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -35,6 +35,11 @@ description: contains a specific memory layout, which is documented in chapter 8 of the SiFive U5 Coreplex Series Manual . + While the "thead,c900-plic" would mask IRQ with readl(claim), so it needn't + mask/unmask which needed in RISC-V PLIC. When in IRQS_ONESHOT & IRQCHIP_EOI_THREADED + path, unnecessary mask operation would cause a blocking irq bug in thead,c900-plic. + Because when IRQ is disabled in c900, writel(hwirq, claim) would be invalid. + maintainers: - Sagar Kadam - Paul Walmsley @@ -46,6 +51,7 @@ properties: - enum: - sifive,fu540-c000-plic - canaan,k210-plic + - thead,c900-plic - const: sifive,plic-1.0.0 reg: -- 2.25.1