From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F167C433F5 for ; Thu, 14 Oct 2021 08:22:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15128600D4 for ; Thu, 14 Oct 2021 08:22:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230176AbhJNIYe (ORCPT ); Thu, 14 Oct 2021 04:24:34 -0400 Received: from verein.lst.de ([213.95.11.211]:49147 "EHLO verein.lst.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230010AbhJNIYd (ORCPT ); Thu, 14 Oct 2021 04:24:33 -0400 Received: by verein.lst.de (Postfix, from userid 2407) id E172B68B05; Thu, 14 Oct 2021 10:22:24 +0200 (CEST) Date: Thu, 14 Oct 2021 10:22:24 +0200 From: "hch@lst.de" To: "Tian, Kevin" Cc: "hch@lst.de" , Jason Gunthorpe , Jean-Philippe Brucker , "kvm@vger.kernel.org" , "jasowang@redhat.com" , "kwankhede@nvidia.com" , "Jiang, Dave" , "Raj, Ashok" , "corbet@lwn.net" , "parav@mellanox.com" , Alex Williamson , "lkml@metux.net" , "david@gibson.dropbear.id.au" , "dwmw2@infradead.org" , "Tian, Jun J" , "linux-kernel@vger.kernel.org" , "lushenming@huawei.com" , "pbonzini@redhat.com" , "robin.murphy@arm.com" Subject: Re: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO Message-ID: <20211014082224.GA30554@lst.de> References: <20210923112716.GE964074@nvidia.com> <20210923122220.GL964074@nvidia.com> <20210929123630.GS964074@nvidia.com> <20210930220446.GF964074@nvidia.com> <20211001032816.GC16450@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 14, 2021 at 08:13:03AM +0000, Tian, Kevin wrote: > Based on above information my interpretation is that existing > DMA API manages coherency per device and It's not designed for > devices which are coherent in nature but also set PCI no-snoop > for selective traffic. Then the new DMA_ATTR_NO_SNOOP, once > set in dma_map, allows the driver to follow non-coherent > semantics even when the device itself is considered coherent. > > Does it capture the whole story correct? Yes. > > > What I don't really understand is why ARM, with an IOMMU that supports > > > PTE WB, has devices where dev_is_dma_coherent() == false ? > > > > Because no IOMMU in the world can help that fact that a periphal on the > > SOC is not part of the cache coherency protocol. > > but since DMA goes through IOMMU then isn't IOMMU the one who > should decide the final cache coherency? What would be the case > if the IOMMU sets WB while the peripheral doesn't want it? No. And IOMMU deal with address translation, it can't paper over a fact that there is no coherency possible.