From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 842A4C433EF for ; Thu, 14 Oct 2021 08:59:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FE23610EA for ; Thu, 14 Oct 2021 08:59:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230176AbhJNJBP (ORCPT ); Thu, 14 Oct 2021 05:01:15 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17088 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230017AbhJNJAm (ORCPT ); Thu, 14 Oct 2021 05:00:42 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634201917; x=1665737917; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2SfxK57vRWHEZrPMMA/I/4JeY6YI1pn+Pq8lPJzvFYk=; b=a0EIrpuZ3kZN/RYhr9hxd3vFoDUyDvZ82LUiHy9bT346tLZUTxUQJr+1 oR8Jn1pk0oZ5KsgD7dCgN6Kw1zRCYCdS55+SIIQ0CyPnsNp7nfGWGyNxV Pn89q9sKTfhW5/QL2g7LnDJmJzzqtOdS+bP/pqB+RxZbVHVcyn7CypYZQ WbbylQXOXx/fCY/xGwq3FtzUy5aNzZQqadTOND6ligqDPRG0xc1HaYEXg ykqPID+IO+nvgxEfGbigwFC2k2GnXBcQoi4q3aG7BTs/WTdlSixKYQfUQ TG4AsAj7/a8kbXyHNjs1HW0GZp5+mXgxsg0nxIkEvnfMdZwoguPD1Fh3r g==; IronPort-SDR: Qf/lBrOUwB/cqSFaTWYx9GBfFVfLWdJcXkZ5ReUrI1ZMY4Vk2fP2L47p7HGcTgo5UV9QtYw6dA LFOvSEPkDBKgDRbhbF2+aQvr0W8sreSQdUORJzeW825I1RxZA2cYsLkn/o/w/UE1DGD06Ib0P1 RgDFSJT6KaTJqMx4+32RNN0UK8x4Nbox1j+7NtXnkP2VhRp/cjpWTzyQVEh3/pYLz5CPuPk4eZ tHEFlo+pXLfaQJdS6NY0O5stxQKVOgsXCMlJlRMhJxlwnEvNb+B0LcyqhaLPuCqn1yC3MW4TGa lw8q2Gmxr1cMFLqzOs+gZwll X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="132960570" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Oct 2021 01:58:37 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 14 Oct 2021 01:58:37 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 14 Oct 2021 01:58:35 -0700 From: Horatiu Vultur To: , , , , , , , , , CC: Horatiu Vultur Subject: [PATCH v3 2/2] pinctrl: microchip sgpio: use reset driver Date: Thu, 14 Oct 2021 10:59:29 +0200 Message-ID: <20211014085929.2579695-3-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211014085929.2579695-1-horatiu.vultur@microchip.com> References: <20211014085929.2579695-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On lan966x platform when the switch gets reseted then also the sgpio gets reseted. The fix for this is to extend also the sgpio driver to call the reset driver which will be reseted only once by the first driver that is probed. Signed-off-by: Horatiu Vultur --- drivers/pinctrl/pinctrl-microchip-sgpio.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index 072bccdea2a5..e8a91d0824cb 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "core.h" #include "pinconf.h" @@ -803,6 +804,7 @@ static int microchip_sgpio_probe(struct platform_device *pdev) int div_clock = 0, ret, port, i, nbanks; struct device *dev = &pdev->dev; struct fwnode_handle *fwnode; + struct reset_control *reset; struct sgpio_priv *priv; struct clk *clk; u32 val; @@ -813,6 +815,10 @@ static int microchip_sgpio_probe(struct platform_device *pdev) priv->dev = dev; + reset = devm_reset_control_get_shared(&pdev->dev, "switch"); + if (!IS_ERR(reset)) + reset_control_reset(reset); + clk = devm_clk_get(dev, NULL); if (IS_ERR(clk)) return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); -- 2.33.0