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From:   Chris Packham <chris.packham@alliedtelesis.co.nz>
To:     andrew@lunn.ch, gregory.clement@bootlin.com,
        sebastian.hesselbarth@gmail.com, robh+dt@kernel.org
Cc:     linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Chris Packham <chris.packham@alliedtelesis.co.nz>
Subject: [PATCH v2 1/2] arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRB
Date:   Mon, 18 Oct 2021 14:12:10 +1300
Message-Id: <20211018011211.3836590-2-chris.packham@alliedtelesis.co.nz>
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Enable the CP0 GPIO devices for the CN9130-CRB. This is needed for a
number of the peripheral devices to function.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Change in v2:
- New

 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boo=
t/dts/marvell/cn9130-crb.dtsi
index e7918f325646..0885c6339d1b 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -17,6 +17,8 @@ aliases {
 		ethernet0 =3D &cp0_eth0;
 		ethernet1 =3D &cp0_eth1;
 		ethernet2 =3D &cp0_eth2;
+		gpio1 =3D &cp0_gpio1;
+		gpio2 =3D &cp0_gpio2;
 	};
=20
 	memory@0 {
@@ -114,6 +116,14 @@ cp0_spi0_pins: cp0-spi-pins-0 {
 	};
 };
=20
+&cp0_gpio1 {
+	status =3D "okay";
+};
+
+&cp0_gpio2 {
+	status =3D "okay";
+};
+
 &cp0_i2c0 {
 	pinctrl-names =3D "default";
 	pinctrl-0 =3D <&cp0_i2c0_pins>;
--=20
2.33.0