From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B956C433FE for ; Wed, 20 Oct 2021 09:05:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2546861359 for ; Wed, 20 Oct 2021 09:05:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229878AbhJTJHt (ORCPT ); Wed, 20 Oct 2021 05:07:49 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:64394 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229503AbhJTJHr (ORCPT ); Wed, 20 Oct 2021 05:07:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634720733; x=1666256733; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=SPBHRwKBxvfeQCeCmvDTAwkvWtsrV8f0sXTIZMWaKDY=; b=fClDs0tklzCV6T9cwNiwpE8J/vOsMJAzTlNp5j1KeyMMLx3B4+jGcIUK OqzmpSNw/f7bePq2gM1xzXRyof34GC61du8WbT44RfQmTjqa+NcI46neJ QuNawZ1doHyFAjSVNMAVT5dfA75C7MK7lIe618f/zgDv/7ATUddnzF6Za ceSg7vGAXxifMBHuLcYQ8DCXv4xRupiP+pCVjskO753h1ftgjjKbN3WZy 09Zo2uUNq4lJSeXL83jRvW4tvIdhS3ya2nS6fuujnkVv7yYcPmz7fgqGH VFbfsyn8QVo46iuKENj1U0f6pn/bOLhSR1jO4IiEv5q4JmFIsw/PLx7AQ w==; IronPort-SDR: 1pFKrgr3bw/cD8VgF6LVGGpsUgQ4qlBePFX9+Pwksym38UqtHCVtAFSVTjF+FQ6lyZF2+m+NL6 KwyHb7ZIShBdIxrbey0uQeKcUvgan2Lb7tdjekeE+Cv9tAlg5LjpdE+3XHCVJU7K6YKx+CwsZV ccZ0GpndddJh6ThIXmNIF63AeyJT7HZ3qyd3Bho4jWl5+SsLbti+C4seLq0930kGA/XI77z4Tw QBGaSQNRmdUKBB2Cd0eIPgAcSfqhi4m3PVvIeV7ItmNRC4EcmW02Nx0j64jECb7TXAY/BaBoDR dBzQRkBDsNo+miaFyxr+friS X-IronPort-AV: E=Sophos;i="5.87,166,1631602800"; d="scan'208";a="141010436" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Oct 2021 02:05:30 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 20 Oct 2021 02:05:30 -0700 Received: from localhost (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 20 Oct 2021 02:05:29 -0700 Date: Wed, 20 Oct 2021 11:07:03 +0200 From: Horatiu Vultur To: Rob Herring CC: Kishon Vijay Abraham I , Vinod , Andrew Lunn , Alexandre Belloni , , , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v3 2/3] dt-bindings: phy: Add constants for lan966x serdes Message-ID: <20211020090703.sspta6qltdymylig@soft-dev3-1.localhost> References: <20211015123920.176782-1-horatiu.vultur@microchip.com> <20211015123920.176782-3-horatiu.vultur@microchip.com> <20211019091258.3uet6lp3mxaoliqt@soft-dev3-1.localhost> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The 10/19/2021 08:38, Rob Herring wrote: > > On Tue, Oct 19, 2021 at 4:11 AM Horatiu Vultur > wrote: > > > > The 10/18/2021 14:28, Rob Herring wrote: > > > > > > On Fri, Oct 15, 2021 at 02:39:19PM +0200, Horatiu Vultur wrote: > > > > Lan966x has: 2 integrated PHYs, 3 SerDes and 2 RGMII interfaces. Which > > > > requires to be muxed based on the HW representation. > > > > > > > > So add constants for each interface to be able to distinguish them. > > > > > > > > Signed-off-by: Horatiu Vultur > > > > --- > > > > include/dt-bindings/phy/phy-lan966x-serdes.h | 14 ++++++++++++++ > > > > 1 file changed, 14 insertions(+) > > > > create mode 100644 include/dt-bindings/phy/phy-lan966x-serdes.h > > > > > > > > diff --git a/include/dt-bindings/phy/phy-lan966x-serdes.h b/include/dt-bindings/phy/phy-lan966x-serdes.h > > > > new file mode 100644 > > > > index 000000000000..8a05f93ecf41 > > > > --- /dev/null > > > > +++ b/include/dt-bindings/phy/phy-lan966x-serdes.h > > > > @@ -0,0 +1,14 @@ > > > > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > > > > + > > > > +#ifndef __PHY_LAN966X_SERDES_H__ > > > > +#define __PHY_LAN966X_SERDES_H__ > > > > + > > > > +#define PHY(x) (x) > > > > +#define PHY_MAX PHY(2) > > > > +#define SERDES6G(x) (PHY_MAX + 1 + (x)) > > > > +#define SERDES6G_MAX SERDES6G(3) > > > > +#define RGMII(x) (SERDES6G_MAX + 1 + (x)) > > > > +#define RGMII_MAX RGMII(2) > > > > +#define SERDES_MAX (RGMII_MAX + 1) > > > > > > I still don't understand. #phy-cells description says we have: > > > > > > > > > > > > But here it's 3 numbers. How are these defines used to fill in the 2 > > > cells? > > > > Actually they are still only a number. Or maybe I am missing something. > > So all the defines apply to the 2nd cell? That's what's missing. Exactly. > The cell description needs to spell all this out. 3 different modes or > whatever. Explain what the h/w is comprised of in the top level > 'description'. I will add this description. > > > > > Maybe an example will help: > > > > --- > > serdes: serdes@e2004010 { > > compatible = "microchip,lan966x-serdes"; > > reg = <0xe202c000 0x9c>, <0xe2004010 0x4>; > > #phy-cells = <2>; > > }; > > > > &port0 { > > ... > > phys = <&serdes 0 SERDES6G(1)>; > > ... > > }; > > > > &port1 { > > ... > > phys = <&serdes 1 PHY(0)>; > > I think CU was better, just needed some comments. PHY is pretty vague. Same here, I will update it. > > > ... > > } > > > > ... > > --- > > > > Here are some existing examples based on which I have created this patch > > series: > > https://elixir.bootlin.com/linux/v5.15-rc6/source/arch/mips/boot/dts/mscc/ocelot_pcb120.dts#L99 > > None of which use PHY() or RGMII()... > > > > https://elixir.bootlin.com/linux/v5.15-rc6/source/arch/mips/boot/dts/mscc/ocelot.dtsi#L274 > > > > > > > > Rob > > > > -- > > /Horatiu -- /Horatiu