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Thu, 21 Oct 2021 05:30:24 -0700 From: Prathamesh Shete To: , , , , , , CC: , Subject: [PATCH 1/2] dt-bindings: tegra186-gpio: Add Tegra234 ports Date: Thu, 21 Oct 2021 18:00:20 +0530 Message-ID: <20211021123021.9602-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6b530077-9d41-408b-0389-08d9948e91be X-MS-TrafficTypeDiagnostic: CH2PR12MB3975: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LnsnnbyZBrOp/oWGNn3ShgEQlaFLFC0Ybw4SkxDr79r64B0eKzbfdQ29hYWcHdvW5/GDgkfD8PGj6YJNwE9mq1HmgAjOTmgJ4p9UqxcUC4fubls4eDuLEIKsYOt6GGjBRJ3kxsMQ1i9ax+PP2/o/uQH2d16yh1+Ji7Yvjafiur3n8+b/xTJQbumG1rv4NNYA86FfAeeuGBb7gKZRCsDPKowqF8Na1P3f1WyRxYwvwdTw4DRVHzdNJTDpKthCbMuxwbHcAyUWX15nhb0jGUyZ9bNHIO1cDTkHX+eUQccTq92NrpgWZTOQ7kCHLEoXwLyI5f+uVRpIrO+yofsDNJXOyEpBOzZQOVnNr+NTB5VWCoV6hYiZeVxnL16566NgU26LHDPzjAPJ4BJ2NqU0LRGC619uAIkWvN1JOncPWeQfSwNtFWrUm2iUZJX6wea5EHhmZ90S2xsu5af7w/KFxIpz5F8EYhrNTp8OCZo8F89nMBSCSjMJDMR3w00hKY6S1EIbF+fcU9rS3nBdy6+T6zTZCzTOcG8v906aj946hyz77BJmYgETezCa/BSisDWbeOUL8DmyPHutiJJ4G+rXEO6PEC4VzPcF8HFhE0oIYJli/Te3c0i4OfidVha8YVRe/7rAlu0em2hk6/nbvzAaDeJk33AlJO6miA+L8A0U5VumAJj2RwOgW7IOPyM/fcxKtioJA4agyvc8wiV/GrNhVmvtdg== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(5660300002)(316002)(8676002)(356005)(7696005)(70206006)(47076005)(336012)(186003)(36860700001)(26005)(4326008)(110136005)(86362001)(6666004)(2906002)(107886003)(8936002)(70586007)(36756003)(82310400003)(54906003)(426003)(508600001)(2616005)(7636003)(1076003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2021 12:30:29.9362 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b530077-9d41-408b-0389-08d9948e91be X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3975 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Tegra234 GPIO ports in dt-bindings. Signed-off-by: Prathamesh Shete --- include/dt-bindings/gpio/tegra234-gpio.h | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 include/dt-bindings/gpio/tegra234-gpio.h diff --git a/include/dt-bindings/gpio/tegra234-gpio.h b/include/dt-bindings/gpio/tegra234-gpio.h new file mode 100644 index 000000000000..0f59afabfe80 --- /dev/null +++ b/include/dt-bindings/gpio/tegra234-gpio.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */ + +/* + * This header provides constants for binding nvidia,tegra234-gpio*. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H + +#include + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA234_MAIN_GPIO_PORT_A 0 +#define TEGRA234_MAIN_GPIO_PORT_B 1 +#define TEGRA234_MAIN_GPIO_PORT_C 2 +#define TEGRA234_MAIN_GPIO_PORT_D 3 +#define TEGRA234_MAIN_GPIO_PORT_E 4 +#define TEGRA234_MAIN_GPIO_PORT_F 5 +#define TEGRA234_MAIN_GPIO_PORT_G 6 +#define TEGRA234_MAIN_GPIO_PORT_H 7 +#define TEGRA234_MAIN_GPIO_PORT_I 8 +#define TEGRA234_MAIN_GPIO_PORT_J 9 +#define TEGRA234_MAIN_GPIO_PORT_K 10 +#define TEGRA234_MAIN_GPIO_PORT_L 11 +#define TEGRA234_MAIN_GPIO_PORT_M 12 +#define TEGRA234_MAIN_GPIO_PORT_N 13 +#define TEGRA234_MAIN_GPIO_PORT_P 14 +#define TEGRA234_MAIN_GPIO_PORT_Q 15 +#define TEGRA234_MAIN_GPIO_PORT_R 16 +#define TEGRA234_MAIN_GPIO_PORT_X 17 +#define TEGRA234_MAIN_GPIO_PORT_Y 18 +#define TEGRA234_MAIN_GPIO_PORT_Z 19 +#define TEGRA234_MAIN_GPIO_PORT_AC 20 +#define TEGRA234_MAIN_GPIO_PORT_AD 21 +#define TEGRA234_MAIN_GPIO_PORT_AE 22 +#define TEGRA234_MAIN_GPIO_PORT_AF 23 +#define TEGRA234_MAIN_GPIO_PORT_AG 24 + +#define TEGRA234_MAIN_GPIO(port, offset) \ + ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset) + +/* GPIOs implemented by AON GPIO controller */ +#define TEGRA234_AON_GPIO_PORT_AA 0 +#define TEGRA234_AON_GPIO_PORT_BB 1 +#define TEGRA234_AON_GPIO_PORT_CC 2 +#define TEGRA234_AON_GPIO_PORT_DD 3 +#define TEGRA234_AON_GPIO_PORT_EE 4 +#define TEGRA234_AON_GPIO_PORT_GG 5 + +#define TEGRA234_AON_GPIO(port, offset) \ + ((TEGRA234_AON_GPIO_PORT_##port * 8) + offset) + +#endif -- 2.17.1