From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50F6BC433FE for ; Thu, 21 Oct 2021 15:58:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B7C56108E for ; Thu, 21 Oct 2021 15:58:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231872AbhJUQAf (ORCPT ); Thu, 21 Oct 2021 12:00:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:59818 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231849AbhJUQAb (ORCPT ); Thu, 21 Oct 2021 12:00:31 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7965B611F2; Thu, 21 Oct 2021 15:58:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1634831895; bh=L8SsVdAZqmcgc/l54J3ELRGN7EmFDhRqTkhV3QJ2iKQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=g68FH0cq70aXjdoLx1elPMm198APq1afbrCj255hNtE16R57d8oXEDmN7iTTXrpTW b9j+sr38KKZXJI8hErEfOfBkZPSwM8wXM+XVw9Ans7H1LmqDGws8Bt061fGGwjpKr5 yY9n9zmu1e5y2pboT41A4tSMKzkRUNymNPE6ftIrcIpAvU3vm2pmgwtlEFfgjJxoQO DBWNCZFk3Wo6qxHitCTMYnAUlXtiQ9ceUqtvEAQPjO9jx/20veksxxDjZ8NrxEsq5h NtwIwY2i9gGtMiQQrZFGkXwUnTo51SirTAeX5kW80tDOcCXgxQWlpwVHGfdXNMfXkS MytNmg154KS0A== Received: by pali.im (Postfix) id 20E5C85E; Thu, 21 Oct 2021 17:58:13 +0200 (CEST) Date: Thu, 21 Oct 2021 17:58:12 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Naveen Naidu Cc: bhelgaas@google.com, linux-kernel-mentees@lists.linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, skhan@linuxfoundation.org, Thomas Petazzoni , Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , "moderated list:PCI DRIVER FOR AARDVARK (Marvell Armada 3700)" Subject: Re: [PATCH v3 11/25] PCI: aardvark: Remove redundant error fabrication when device read fails Message-ID: <20211021155812.qwihgqo6dk73433w@pali> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20180716 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 21 October 2021 20:37:36 Naveen Naidu wrote: > An MMIO read from a PCI device that doesn't exist or doesn't respond > causes a PCI error. There's no real data to return to satisfy the > CPU read, so most hardware fabricates ~0 data. > > The host controller drivers sets the error response values (~0) and > returns an error when faulty hardware read occurs. But the error > response value (~0) is already being set in PCI_OP_READ and > PCI_USER_READ_CONFIG whenever a read by host controller driver fails. > > Thus, it's no longer necessary for the host controller drivers to > fabricate any error response. > > This helps unify PCI error response checking and make error check > consistent and easier to find. > > Signed-off-by: Naveen Naidu Reviewed-by: Pali Rohár > --- > drivers/pci/controller/pci-aardvark.c | 10 ++-------- > 1 file changed, 2 insertions(+), 8 deletions(-) > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > index 596ebcfcc82d..1af772c76d06 100644 > --- a/drivers/pci/controller/pci-aardvark.c > +++ b/drivers/pci/controller/pci-aardvark.c > @@ -893,10 +893,8 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, > u32 reg; > int ret; > > - if (!advk_pcie_valid_device(pcie, bus, devfn)) { > - *val = 0xffffffff; > + if (!advk_pcie_valid_device(pcie, bus, devfn)) > return PCIBIOS_DEVICE_NOT_FOUND; > - } > > if (pci_is_root_bus(bus)) > return pci_bridge_emul_conf_read(&pcie->bridge, where, > @@ -920,7 +918,6 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, > *val = CFG_RD_CRS_VAL; > return PCIBIOS_SUCCESSFUL; > } > - *val = 0xffffffff; > return PCIBIOS_SET_FAILED; > } > > @@ -955,16 +952,13 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, > *val = CFG_RD_CRS_VAL; > return PCIBIOS_SUCCESSFUL; > } > - *val = 0xffffffff; > return PCIBIOS_SET_FAILED; > } > > /* Check PIO status and get the read result */ > ret = advk_pcie_check_pio_status(pcie, allow_crs, val); > - if (ret < 0) { > - *val = 0xffffffff; > + if (ret < 0) > return PCIBIOS_SET_FAILED; > - } > > if (size == 1) > *val = (*val >> (8 * (where & 3))) & 0xff; > -- > 2.25.1 >