From: Paul Cercueil <paul@crapouillou.net>
To: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Sam Ravnborg <sam@ravnborg.org>,
"H . Nikolaus Schaller" <hns@goldelico.com>,
Paul Boddie <paul@boddie.org.uk>,
list@opendingux.net, linux-mips@vger.kernel.org,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Paul Cercueil <paul@crapouillou.net>
Subject: [RESEND PATCH v3 4/6] drm/ingenic: Set DMA descriptor chain register when starting CRTC
Date: Tue, 26 Oct 2021 19:12:38 +0100 [thread overview]
Message-ID: <20211026181240.213806-5-paul@crapouillou.net> (raw)
In-Reply-To: <20211026181240.213806-1-paul@crapouillou.net>
Setting the DMA descriptor chain register in the probe function has been
fine until now, because we only ever had one descriptor per foreground.
As the driver will soon have real descriptor chains, and the DMA
descriptor chain register updates itself to point to the current
descriptor being processed, this register needs to be reset after a full
modeset to point to the first descriptor of the chain.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 5dbeca0f8f37..cbc76cede99e 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -186,6 +186,10 @@ static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
+ /* Set address of our DMA descriptor chain */
+ regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, 0));
+ regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1));
+
regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
JZ_LCD_CTRL_ENABLE);
--
2.33.0
next prev parent reply other threads:[~2021-10-26 18:13 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-26 18:12 [RESEND PATCH v3 0/6] drm/ingenic: Various improvements v3 Paul Cercueil
2021-10-26 18:12 ` [RESEND PATCH v3 1/6] drm/ingenic: Simplify code by using hwdescs array Paul Cercueil
2021-10-29 16:54 ` Christophe Branchereau
2021-10-26 18:12 ` [RESEND PATCH v3 2/6] drm/ingenic: Add support for private objects Paul Cercueil
2021-10-29 16:55 ` Christophe Branchereau
2021-10-26 18:12 ` [RESEND PATCH v3 3/6] drm/ingenic: Move IPU scale settings to private state Paul Cercueil
2021-10-29 16:55 ` Christophe Branchereau
2021-10-26 18:12 ` Paul Cercueil [this message]
2021-10-29 16:55 ` [RESEND PATCH v3 4/6] drm/ingenic: Set DMA descriptor chain register when starting CRTC Christophe Branchereau
2021-10-26 18:12 ` [RESEND PATCH v3 5/6] drm/ingenic: Upload palette before frame Paul Cercueil
2021-10-29 16:55 ` Christophe Branchereau
2021-10-26 18:12 ` [RESEND PATCH v3 6/6] drm/ingenic: Attach bridge chain to encoders Paul Cercueil
2021-10-29 16:55 ` Christophe Branchereau
2021-10-29 20:47 ` Paul Cercueil
2021-10-26 18:50 ` [RESEND PATCH v3 0/6] drm/ingenic: Various improvements v3 H. Nikolaus Schaller
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