From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, tglx@linutronix.de, dave.hansen@linux.intel.com,
peterz@infradead.org, bp@alien8.de, mingo@redhat.com,
chang.seok.bae@intel.com
Subject: [PATCH 3/4] x86/fpu: Prepare AMX state for CPU idle
Date: Thu, 4 Nov 2021 15:52:25 -0700 [thread overview]
Message-ID: <20211104225226.5031-4-chang.seok.bae@intel.com> (raw)
In-Reply-To: <20211104225226.5031-1-chang.seok.bae@intel.com>
Before entering CPU idle, make sure large registers such as AMX TILE are
initialized. Otherwise, non-initialized register states may prevent a CPU
from entering a deeper low-power state.
Suggested-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
---
arch/x86/kernel/process.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index eb470be0e5ae..7044ba276064 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -707,6 +707,7 @@ static inline void play_dead(void)
void arch_cpu_idle_enter(void)
{
+ fpu_idle_fpregs();
tsc_verify_tsc_adjust(false);
local_touch_nmi();
}
--
2.17.1
next prev parent reply other threads:[~2021-11-04 23:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-04 22:52 [PATCH 0/4] x86/fpu: Make AMX state ready for CPU idle Chang S. Bae
2021-11-04 22:52 ` [PATCH 1/4] x86/insn/amx: Add TILERELEASE instruction to the opcode map Chang S. Bae
2021-11-04 22:52 ` [PATCH 2/4] x86/fpu: Add a helper to prepare AMX state for CPU idle Chang S. Bae
2021-11-04 22:52 ` Chang S. Bae [this message]
2021-11-04 22:52 ` [PATCH 4/4] intel_idle: Add SPR support with AMX INIT-state Chang S. Bae
2021-11-05 14:33 ` Thomas Gleixner
2021-11-05 16:03 ` Bae, Chang Seok
2021-11-05 17:26 ` Thomas Gleixner
2022-03-09 22:44 ` Chang S. Bae
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